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Portland State University

Logic synthesis

1999

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Full-Text Articles in Engineering

Logic Synthesis For A Regular Layout, Marek Perkowski, Yang Xu, Malgorzata Chrzanowska-Jeske Jan 1999

Logic Synthesis For A Regular Layout, Marek Perkowski, Yang Xu, Malgorzata Chrzanowska-Jeske

Electrical and Computer Engineering Faculty Publications and Presentations

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits …