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Atpg For Reversible Circuits Using Technology-Related Fault Models, Jeff S. Allen, Jacob D. Biamonte, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

We address the problem of test set generation and test set reduction, to first detect, and later localize faults occurring in reversible circuits. Reversible Computation has high promise of low power consumption. Some new fault models are first presented here. An explanation of the new fault models is made based on a physical realization representing the state of the art in the reversible CMOS circuit technology. Evidence is then presented showing that the fault models presented in the current literature are not adequate for existing realizations of reversible logic such as CMOS. We designed a ATPG software package with a …