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High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy
High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy
Dissertations and Theses
This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit …
The Object-Oriented Design Of A Hardware Description Language Analyser For The Diades Silicon Compiler System, Lian Yang
Dissertations and Theses
This thesis is one of the first to introduce a systematic and general Source Language Analysis System (called SLA) for a high -level synthesis system.