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Design Of Low Phase Drift Cmos Frequency Synthesisers, Cyril Patrick Hervé Florent Lahuec

Theses

This thesis presents a methodology for the development of high performance video clock synthesisers that have high (2000) input to output clock multiplication ratios. The synthesisers are required to be compatible with standard CMOS technologies and they must exhibit very low drift between their input and output clocks.

The methodology used borrows techniques established for RF synthesisers in the GHz range. In the RF domain there are significant constraints on spectral spread and because of this there has been significant interest in phase noise generated by intrinsic device noise. Simple and accurate models were developed that help understand the up …