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Duplicate With Choose: Using Statistics For Fault Mitigation, Jon-Paul Anderson
Duplicate With Choose: Using Statistics For Fault Mitigation, Jon-Paul Anderson
Theses and Dissertations
This dissertation presents a novel technique called duplicate with choose (DWCh) which is a modification of the fault detection technique duplicate with compare (DWC). DWCh adds a smart decider block to DWC that monitors the duplicated circuits and decides which circuit is fault free when a fault occurs. If chosen correctly, DWCh is able to mask faults at a lower cost than conventional techniques like TMR.This dissertation derives reliability expressions for DWCh showing that under ideal conditions its reliability exceeds the most commonly used fault masking technique for spacecraft, triple modular redundancy. For non-ideal conditions, DWCh provides a lower cost …
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Theses and Dissertations
Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's …
Using Source-To-Source Transformations To Add Debug Observability To Hls-Synthesized Circuits, Joshua Scott Monson
Using Source-To-Source Transformations To Add Debug Observability To Hls-Synthesized Circuits, Joshua Scott Monson
Theses and Dissertations
This dissertation introduces a novel approach for exposing the internal, source-level expressions of circuits generated by high-level synthesis (HLS) for in-circuit debug. The approach uses source-to-source transformations to instrument specific source-level expressions with debug ports. These debug ports allow a user to connect a debugging instrument (e.g. an embedded logic analyzer) to record the activity of the expression corresponding to the debug port. This dissertation demonstrates that a debugging solution based on these source-to-source transformations is feasible and that individual debug ports can be added for a cost of a 1-2% increase in circuit area on average. It also introduces …