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Full-Text Articles in Engineering
A Numerical Study Of High-Speed Missile Configurations Using A Block- Structured Parallel Algorithm, Douglas C. Blake
A Numerical Study Of High-Speed Missile Configurations Using A Block- Structured Parallel Algorithm, Douglas C. Blake
Theses and Dissertations
A numerical analysis of the aerodynamic phenomena associated with the high-speed flight of a sharp-nosed, four-finned, high-fineness ratio missile using a block-structured, parallel computer algorithm is presented. The algorithm, PANS-3EM, utilizes a second-order-accurate, shock-capturing, Total Variation Diminishing scheme and incorporates a Baldwin-Lomax turbulence model. PANS-3EM allows for extreme flexibility in the choice of computational domain decomposition and computing machine of implementation. Developmental work consists of conceptualization and verification of the algorithm as well as parallel performance and scalability studies conducted on a variety of computing platforms. Using PANS-3EM, the aerodynamic characteristics of the missile are investigated. Drag and pitching moment …
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
Interactive Control Of A Parallel Simulation From A Remote Graphics Workstation, Douglas C. Looney
Interactive Control Of A Parallel Simulation From A Remote Graphics Workstation, Douglas C. Looney
Theses and Dissertations
Modern military commanders are faced with an overwhelming amount of intelligence data concerning the disposition of engaging forces, The sheer volume of data produced for a single planning scenario is an obstacle to the user as well as the computer. Today’s commander requires a real-time, three- dimensional representation of the battlefield in order to assimilate the data for the management of a conflict. Parallel computation is required to complete the processing of this information in a timely manner. A network protocol is required to link the interface with the parallel simulation. The of this study is to improve user interaction …
Genetic Algorithms Applied To A Mission Routing Problem, James B. Olsan
Genetic Algorithms Applied To A Mission Routing Problem, James B. Olsan
Theses and Dissertations
This thesis applies genetic algorithms to a mission routing problem. The mission routing problem involves determining an aircraft’s best route between a staging base and a target. The goal is to minimize the route distance and the exposure to radar. Potential routes are mapped to a 3-dimensional mesh where the nodes correspond to checkpoints in the route and the arcs correspond to partial paths of the route. Each arc is weighted with respect to distance and exposure to radar. A genetic algorithm is a probabilistic search technique loosely based on theories of biological evolution. Genetic crossover and survival of the …
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Theses and Dissertations
A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design …