Engineering Commons^™

A Case Study In Cmos Design Scaling For Analog Applications: The Ringamp Ldo, Steven Corum

Masters Theses

As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog …

Design Of A Sigma-Delta Adc In 65nm Cmos Process, Michael Lee Thompson Iii

Electrical Engineering Undergraduate Honors Theses

Analog and digital signals both play a vital role in electrical engineering and the technology of today. As the role of electrical and computer engineers becomes more deeply involved in the development of new technology, an understanding of how these signals are utilized, and what they represent, is a necessity. Due to the inherent limitations involved with analog signals, there is a need for these signals to be accurately and efficiently converted to digital signals for processing. The job of the analog-to-digital converter, or ADC, is to receive this analog input signal (voltage or current) and create a digital representation …

A Low-Power, Low-Area 10-Bit Sar Adc With Length-Based Capacitive Dac, Zhili Pan

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 µm^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the …

Etching Process Development For Sic Cmos, Weston Reed Renfrow

Graduate Theses and Dissertations

Silicon Carbide (SiC) is an exciting material that is growing in popularity for having qualities that make it a helpful semiconductor in extreme environments where silicon devices fail. The development of a SiC CMOS is in its infancy. There are many improvements that need to be made to develop this technology further. Photolithography is the most significant bottleneck in the etching process; it was studied and improved upon. Etching SiC can be a challenge with its reinforced crystal structure. Chlorine-based inductively coupled plasma (ICP) etching of intrinsic SiC and doped SiC, SiO2, and Silicon has been studied. A baseline chlorine …

Cmos Compatible Carbonization Of Polymer For Elctrochemical Sensors, Mohammad Aminul Haque

Doctoral Dissertations

Carbon-based electrodes that are integrable with CMOS readout electrodes possess great potential in a wide range of cutting-edge applications. The primary scientific contribution is the development of a processing sequence which can be implemented on CMOS chips to fabricate pyrolyzed carbon microelectrodes from 3D printed polymer microstructures to develop lab-on-CMOS monolithic electrochemical sensor systems. Specifically, optimized processing conditions to convert 3D printed polymer micro- and nano-structures to carbonized electrodes have been explored in order to obtain sensing electrodes for lab-on- CMOS electrochemical systems. Processing conditions have been identified, including a sequel of oxidative and inert atmosphere anneals to form pyrolyzed …

A Ringamp-Assisted, Output Capacitor-Less Analog Cmos Low-Dropout Voltage Regulator, Jordan Sangid

Doctoral Dissertations

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) …

Phase Noise Analyses And Measurements In The Hybrid Memristor-Cmos Phase-Locked Loop Design And Devices Beyond Bulk Cmos, Naheem Olakunle Adesina

LSU Doctoral Dissertations

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.

Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, …

Cascading Cmos-Based Chaotic Maps For Improved Performance And Its Application In Efficient Rng Design, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain, Barry Muldrey, Md Sakib Hasan

Faculty and Student Publications

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 $nm$ designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and …

Memory Module Design For High-Temperature Applications In Sic Cmos Technology, Affan Abbasi

Graduate Theses and Dissertations

The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is …

Design And Implementation Of A Multi-Modal Sensor With On-Chip Security, Ava Hedayatipour

Doctoral Dissertations

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore's law and …

Electrospun Nanofibrous Membrane Based Glucose Sensor With Integration Of Potentiostat Circuit, Kavyashree Puttananjegowda

USF Tampa Graduate Theses and Dissertations

Although wearable and portable biomedical devices are the pillar of modern and smart societies, a large portion the device infrastructure is still under development, operates with poor monitoring and automation, and lacks sufficient communication among components. Moreover, demand for wearable bio-medical devices is expected to increase in the coming years. This situation presents a unique opportunity for electrical engineers to design novel strategies that allow point-of-care diagnostics to satisfy the increasing demand of wearable bio-medical devices. For example, in the medical field there is a rising diabetic population base, high demand for miniature and low-power diagnostic devices, and the need …

Energy Efficiency In Cmos Power Amplifier Designs For Ultralow Power Mobile Wireless Communication Systems, Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Harikrishnan Ramiah, Asrulnizam Abd Manaf

Turkish Journal of Electrical Engineering and Computer Sciences

Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49 % of the overall efficiency from the transmitter. Hence, operating the PA …

5-Bit Dual-Slope Analog-To-Digital Converter-Based Time-To-Digital Converter Chip Design In Cmos Technology, Jojoe S. Sagoe

LSU Master's Theses

Time-to-Digital Converters (TDC) have gained increasing importance in modern implementations of mixed-signal, data-acquisition and processing interfaces and are used to perform high precision time intervals in systems that incorporate Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurements. The linearity of TDCs is very crucial since most Digital Signal Processing (DSP) systems require very linear inputs to achieve high accuracy.

In this work, a TDC has been designed in the 0.5 μm n-well CMOS process that can be used for on-chip integration and in applications requiring high linearity. This TDC used a Dual-Slope-ADC-based architecture for the time-to-digital conversion and consists of the following …

Modified Recycling Folded Cascode Ota With Enhancement In Transconductance And Output Impedance, Sudheer Raja Venishetty, Kumaravel Sundaram

Turkish Journal of Electrical Engineering and Computer Sciences

A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 $\mu$A. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it …

Cmos Receiver Design For 802.11ac Standard Using Offline Calibrated Active Inductor Based Band Pass Filter In 90 Nm Technology, Shuo Li

Browse all Theses and Dissertations

Wireless local area network is widely used in industry and people daily life. More and more mobile devices rely on this technology to perform data communication with 2.4 GHz and 5 GHz frequency band. As the development of CMOS technology is able to keep shrinking chip size and increasing circuit integration density, traditional on-chip passive inductor inefficient area consumption issue is becoming critical to receiver front end system design. In this dissertation, an active inductor-based band pass filter is studied and implemented with 90 nm technology. This active inductor design provides very small area consumption and larger quality factor compared …

Cmos Radioactive Isotope Identification With Multichannel Analyzer And Embedded Neural Network, Samuel Murray

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A radiation detection and identification system is designed and implemented to perform gamma ray spectroscopy on radioactive sources and identify which isotopes are present in the sources. A multichannel analyzer is implemented on an ASIC to process the signal produced from gamma rays detected by a scintillator and photomultiplier tube and to quantize the gamma ray energies to build a histogram. A fast, low memory embedded neural network is implemented on a microcontroller ASIC to identify the isotopes present in the gamma ray histogram produced by the multichannel analyzer in real time.

Advisors: Sina Balkir and Michael Hoffman

An Analog Cmos Particle Filter, Trevor Watson

Masters Theses

Particle filters are used in a variety of image processing and machine learning applications. Their main use in these applications is to gather information about a system of objects, by using partial or noisy observations collected from sensors. These observations are used to associate points of interest in the observations with objects and maintain this association through a series of observations.

In this paper I will investigate the performance of a particle filter implemented in 130nm analog CMOS hardware. The design goal of the particle filter is low-microwatt power consumption. Using analog hardware, rather than digital ASICs or CPUs I …

Design And Evaluation Of A Sub-1-Volt Read Flash Memory In A Standard 130 Nanometer Cmos Process, David Andrew Basford

Masters Theses

Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI), Fowler-Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the oating-gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented.

Fabrication of ash memory in a standard CMOS process presents significant design challenges. The absence of …

Design And Implementation Of A Low‐Power Wireless Respiration Monitoring Sensor, Ifana Mahbub

Doctoral Dissertations

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit …

Design Of An Active Harmonic Rejection N-Path Filter For Highly Tunable Rf Channel Selection, Craig J. Fischer

Master's Theses

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve …

A Sub-Threshold Low-Power Integrated Bandpass Filter For Highly-Integrated Spectrum Analyzers, Benjamin David Roehrs

Masters Theses

Low-power analog filter banks provide frequency analysis with minimal space requirements, making them viable solutions for integrated remote audio- and vibration-sensing applications. In order to achieve a balance between the length of deployable service and system performance, a critical requirement of such remote sensor networks is low-power consumption, due to the constraints imposed by on-board battery cells.

In this work, the design and implementation of a sub-threshold complementary metal-oxide semiconductor (CMOS) integrated low-power tunable analog filter channel for Oak Ridge National Laboratory is presented. Project specifications required a tunable, high-order, monolithic bandpass filter channel with small chip area and low …

Cmos Programmable Time Control Circuit Design For Phased Array Uwb Ground Penetrating Radar Antenna Beamforming, Nicholas James Reilly

Graduate College Dissertations and Theses

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many …

Electronically Tunable Mos-Only Current-Mode High-Order Band-Pass Filters, Pipat Prommee, Aphinat Tiamsuphat, Muhammad Taher Abuelmaatti

Turkish Journal of Electrical Engineering and Computer Sciences

This paper presents new CMOS current-mode ladder Chebyshev and elliptic band-pass filters (BPFs). The signal flow graph and the network transformation methods are used to synthesize the proposed BPFs by using Chebyshev and elliptic RLC low-pass prototypes. CMOS-based lossy and lossless integrators with grounded capacitors are used to synthesize the proposed BPFs. The proposed filters can be electronically tuned between 10 kHz and 100 MHz by adjusting the bias current from 0.02 $\mu $A to 200 $\mu $A. Both filters use a 1.5 V DC power supply, which leads to low dynamic power consumption. Both filters enjoy total harmonic distortion …

Last Two Surface Range Detector For Direct Detection Multisurface Flash Lidar In 90nm Cmos Technology, Douglas Preston

Browse all Theses and Dissertations

This thesis explores a novel detection architecture for use in a Direct-Detect Flash LIDAR system. The proposed architecture implements detection of the last two surfaces within single pixels of a target scene. The novel, focal plane integrated detector design allows for detection of objects behind sparse and/or partially reflective covering such as forest canopy. The proposed detector would be duplicated and manufactured on-chip behind each avalanche photodiode within a focal plane array. Analog outputs are used to minimize interference from digital components on the analog input signal. The proposed architecture is a low-footprint solution which requires low computational post-processing. Additionally, …

Design, Fabrication And Testing Of Monolithic Low-Power Passive Sigma-Delta Analog-To-Digital Converters, Angsuman Roy

UNLV Theses, Dissertations, Professional Papers, and Capstones

Analog-to-digital converters are critically important in electronic systems. The

difficulty in meeting high performance parameters increases as integrated circuit design

process technologies advance into the deep nanometer region. Sigma-delta analog-todigital

converters are an attractive option to fulfill many data converter requirements.

These data converters offer high performance while relaxing requirements on the precision

of components within an integrated circuit. Despite this, the active integrators found within

sigma-delta analog-to-digital converters present two main challenges. These challenges are

the power consumption of the active amplifier and achieving gain-bandwidth necessary for

sigma-delta data converters in deep nanometer process technologies. Both of these

challenges …

Fault Resilient And Reconfigurable Power Management Using Photovoltaic Integrated With Cmos Switches, Rakeshkumar Mahto

Electrical and Computer Engineering ETDs

A Photovoltaic (PV) cell is a device which converts light incident upon it to electric current. The push for green energy due to global warming and diminution of fossil fuels opens up a huge market for PV cells. Hence, a lot of interest is being garnered for using PV cells for various applications. However, a PV module's performance degrades due to many anomalies such as failure of individual PV cell within a module, the opening of interconnection, a short circuit in the connection, failure of bypass diode, failure in voltage regulator or partial shading. To some extent all of these …

A 2.4-Ghz Highly Linear Derivative Superposition Gilbert Cell Mixer, Samaneh Sedighi, Omid Hashemipour, Massoud Dousti

Turkish Journal of Electrical Engineering and Computer Sciences

This paper presents a new derivative superposition Gilbert cell to minimize the third-order nonlinear current term of transconductance transistors. To decrease the parasitic capacitance effect on gain, noise figure, and linearity of the circuit, extra inductors and capacitors are added between the switching and transconductance stages. The proposed mixer is simulated in 0.18-$\mu $m RF-CMOS technology with a 1.8-V supply. The results show an improvement of about 23 dBm in IIP3 compared to conventional mixers. The power consumption of this circuit is about 3.96 mW.

The Development Of Iii-V Semiconductor Mosfets For Future Cmos Applications, Andrew M. Greene

Legacy Theses & Dissertations (2009 - 2024)

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance …

Study Of Millisecond Laser Annealing On Ion Implanted Soi And Application To Scaled Finfet Technology, Tyler J. Michalak

Legacy Theses & Dissertations (2009 - 2024)

The fabrication of metal-oxide-semiconductor field effect transistors (MOSFET) requires the engineering of low resistance, low leakage, and extremely precise p-n junctions. The introduction of finFET technology has introduced new challenges for traditional ion implantation and annealing techniques in junction design as the fin widths continue to decrease for improved short channel control. This work investigates the use of millisecond scanning laser annealing in the formation of n-type source/drain junctions in next generation MOSFET.

Wideband Automatic Gain Control Design In 130 Nm Cmos Process For Wireless Receiver Applications, Joseph Benito Strzelecki

Browse all Theses and Dissertations

An analog automatic gain control circuit (AGC) and mixer were implemented in 130 nm CMOS technology. The proposed AGC was intended for implementation into a wireless receiver chain. Design specifications required a 60 dB tuning range on the output of the AGC, a settling time within several microseconds, and minimum circuit complexity to reduce area usage and power consumption.

Desired AGC functionality was achieved through the use of four nonlinear variable gain amplifiers (VGAs) and a single LC filter in the forward path of the circuit and a control loop containing an RMS power detector, a multistage comparator, and a …