Engineering Commons^™

Des And Tdes Performance Evaluation For Non-Pipelined And Pipelined Implementations In Vhdl Using The Cyclone Ii Fpga Technology, Edni Del Rosal

Theses and Dissertations

Two ongoing issues that engineers must face in the new era of data analytics are performance and security. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications while the Data Encryption Standard (DES) and the Triple Data Encryption Standard (TDES) offer a mean to secure information. In this thesis we present a Non-Pipelined and Pipelined, in Electronic Code Book (EBC) mode, implementations in VHDL of these two commonly utilized cryptography schemes. Using Altera Cyclone II FPGA as our platform, we design and verify the implementations with the EDA tools provided by Altera. We gather …

Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout

Masters Theses

Since its commissioning in 2006, Spallation Neutron Source (SNS) at Oak Ridge National Laboratory has greatly contributed to the field of neutron science, but some critical systems are reaching end-of-life. This obsolescence must be addressed for the accelerator to continue providing world-class research capabilities. One such system needing redesign is the low-level RF (LLRF) control system for the proton accumulator ring. While this system has performed acceptably for over a decade, it is sparsely documented and robust operational models are unavailable. To ensure the new design meets or exceeds current performance metrics, we analyzed the existing LLRF control system and …

Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart

Masters Theses

Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA neural …

Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young

Masters Theses

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …

Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen

Theses and Dissertations

With a few exceptions, academic packing algorithms for FPGAs are typically applied solely to theoretical architectures. This has allowed the algorithms to focus on the basic components of packing while abstracting away many of the details dictated by real hardware. As commercially available FPGAs have advanced, however, the academic algorithms and architectures have diverged significantly from their commercial counterparts. In this dissertation, the RapidSmith 2 framework is presented. This framework accurately reflects the architecture of Xilinx FPGAs and provides support for integrating custom tools into the commercial CAD tools. Using this framework, the RSVPack packing algorithm is implemented. The RSVPack …

Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend

Theses and Dissertations

The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be extracted …

General-Purpose Digital Filter Platform, Michael Cheng

Electrical Engineering

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a …

Embedded Processors On Fpga: Hard-Core Vs Soft-Core, Vivek J. Vazhoth Kanhiroth

Masters Theses

Field Programmable Gate Arrays (FPGAs) are integrated circuits (ICs) that can be reprogrammed by the consumer after manufacturing. They are based on a matrix of configurable logic blocks connected via programmable interconnects that enables the designer to quickly recreate hardware circuits. In the past, FPGAs were primarily used for prototyping and debugging purposes. However, with their increased popularity, many commercial products now incorporate FPGAs.

In the late 1990s, FPGA vendors introduced System-on-chip (SoC) devices that housed one or more hard-core processors and an FPGA fabric on a single IC to allow for more complex designs that involved hardware and software …

A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah

Graduate Theses and Dissertations

The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …

Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge

Master's Theses (2009 -)

This thesis develops the first fully network-on-chip (NoC) based h.264 video decoder implemented in real hardware on a field programmable gate array (FPGA). This thesis starts with an overview of the h.264 video coding standard and an introduction to the NoC communication paradigm. Following this, a series of processing elements (PEs) are developed which implement the component algorithms making up the h.264 video decoder. These PEs, described primarily in VHDL with some Verilog and C, are then mapped to an NoC which is generated using the CONNECT NoC generation tool. To demonstrate the scalability of the proposed NoC based design, …

Architecture, Simulation, And Implementation Of Commodity Computer Components In Software Defined Radio Systems, Amean Al-Safi

Dissertations

Radio communications have evolved through an extended history of theoretical and practical component development into modern devices most often envisioned as the ubiquitous smart phones found in almost everyone’s hand on a university campus. During this development, radios have evolved from analog devices operating at low frequencies into nearly all digital processing systems referred to as Software Defined Radio (SDR) operating in frequency bands over 1 Gigahertz. Although specific forms and types of communication are fiercely pursued by commercial communication companies and industry, there remain numerous concepts where further advancement is possible, and applications, possibly less commercially viable, where advancements …

Using On-Chip Error Detection To Estimate Fpga Design Sensitivity To Configuration Upsets, Andrew Mark Keller

Theses and Dissertations

SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to …

High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell

Theses and Dissertations

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …

A Reconfigurable Trusted Platform Module, Matthew David James

Theses and Dissertations

A Trusted Platform Module (TPM) is a security device included in most modern desktop and laptop computers. It helps keep the computing environment secure by isolating cryptographic functions and data from the CPU. A TPM is usually implemented with a small microcontroller which is near the main processor. In addition to a microcontroller, it may employ hardware acceleration to assist in cryptographic computations. When vulnerabilities are found, or new algorithms developed, TPMs become obsolete because the hardware accelerators cannot be upgraded. This thesis presents a proof of concept implementation of a TPM on an FPGA. By using an FPGA, the …

Low Trade-Off Security Schemes To Detect And Neutralize Malicious Modifications In Nano-Cmos Based Integrated Circuits, Nagendra Gunti

All ETDs from UAB

Security of Integrated electronics is threatened by the vulnerabilities such as the globalization of the Integrated Circuits (ICs) industry, where a computing chip can be manufactured anywhere in the world. Without trusted foundries, the systems they de- velop cannot necessarily be expected to perform as specified due to the susceptibility to attack by a malicious adversary. The threats which arise from malicious modifica- tions to the IC based computing hardware, can disable the system, leak information or produce malfunctions and also provide a back door entry to embedded systems like Cy- ber Physical System (CPS) or can even deny providing …

Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding

Graduate Theses and Dissertations

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.

In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. …

Fpga Implementation And Study Of Hardware Trojan In A Closed Loop Control System, Ranveer Kumar

All ETDs from UAB

A closed-loop system is a primary technology used to automate our critical infrastructure and major industries to improve their efficiency. Their dependability is challenged by probable vulnerabilities in the core computing system. These vulnerabilities can appear on both front (software) and back (hardware) ends of the computing system. While the software vulnerabilities are well researched and documented, the hardware ones are normally overlooked. However, with hardware-inclusive technological evolutions like Cyber-Physical Systems and Internet-of-Things, hardware vulnerabilities should be addressed appropriately. In this work, we present a study of one such vulnerability, called hardware Trojan (HT), on a closed-loop control system. Since …