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Full-Text Articles in Engineering
Anti-Phishing Approach For Iot System In Fog Networks Based On Machine Learning Algorithms, Mahmoud Gad Awwad, Mohamed M. Ashour, El Said A. Marzouk, Eman Abdelhalim
Anti-Phishing Approach For Iot System In Fog Networks Based On Machine Learning Algorithms, Mahmoud Gad Awwad, Mohamed M. Ashour, El Said A. Marzouk, Eman Abdelhalim
Mansoura Engineering Journal
As the Internet of Things (IoT) continues to expand, ensuring the security and privacyِ of IoT systems becomes increasingly critical. Phishing attacks pose a significant threat to IoT devices and can lead to unauthorized access, data breaches, and compromised functionality. In this paper, we propose an anti-phishing approach for IoT systems in fog networks that leverages machine learning algorithms, including a .fusion with deep learning techniques We explore the effectiveness of eleven traditional machine learning algorithms combined with deep learning in detecting and preventing phishing attacks in IoT systems. By utilizing a diverse range of algorithms, we aim to enhance …
Side Lobe Level Reduction And Array Thinning Of Concentric Circular Antenna Arrays, Alzahraa H. Nosier, Ahmed M. Elkhawaga, Mohamed E. Nasr, Nessim M. Mahmoud, Amr H. Hussein
Side Lobe Level Reduction And Array Thinning Of Concentric Circular Antenna Arrays, Alzahraa H. Nosier, Ahmed M. Elkhawaga, Mohamed E. Nasr, Nessim M. Mahmoud, Amr H. Hussein
Mansoura Engineering Journal
This paper presents a new beamforming technique based on the hybrid combination of the convolution algorithm (CA) and the genetic algorithm (GA) for reducing side lobe level (SLL) and array thinning of concentric circular antenna arrays (CCAA), which is denoted as C/GA technique. The CA determines the excitations of the elements, while the GA optimizes the radii of the circular arrays to adjust the half-power beamwidth (HPBW). For CCAA consisting of uniform feeding circular arrays, we assume that there are excitation coefficients that are distributed symmetrically around the array center and arranged in a vector. The excitation vector is convolved …
Enhancing Network Security In Iot Applications Through Ddos Attack Detection Using Ml, Ahmed Mohamed Salama, Mohamed Abdelazim Mohamed, Eman Abdelhalim
Enhancing Network Security In Iot Applications Through Ddos Attack Detection Using Ml, Ahmed Mohamed Salama, Mohamed Abdelazim Mohamed, Eman Abdelhalim
Mansoura Engineering Journal
A significant issue that affects contemporary network infrastructures is the Distributed Denial of Service (DDoS) attack, which presents serious dangers to organizations, people, and even governments. By flooding a target server, network, or website with deceptive traffic, this kind of cyberattack seeks to prevent it from providing services to legitimate users. For those in charge of maintaining network security, the prevalence and sophistication of these attacks have both grown significantly. DDoS attacks have the potential to lead to significant financial losses and service interruptions. Anomaly-based systems, traffic filtering, and Machine Learning (ML) algorithms are employed to spot them and lessen …
A 10-Gb/S Single-Loop Half-Rate Dll-Based Clock And Data Recovery Circuit For Forwarded-Clock Wireline Transceivers, Abdallah K. Mohamed, Sameh A. Ibrahim, Mohy Eldin A. Abo-Elsoud
A 10-Gb/S Single-Loop Half-Rate Dll-Based Clock And Data Recovery Circuit For Forwarded-Clock Wireline Transceivers, Abdallah K. Mohamed, Sameh A. Ibrahim, Mohy Eldin A. Abo-Elsoud
Mansoura Engineering Journal
This paper introduces a 10-Gb/s single-loop, half-rate delay-locked loop (DLL)-based clock and data recovery (CDR) circuit for forwarded-clock (FC) wireline transceivers. The proposed CDR employs a differential ring oscillator (RO) with sub-feedback loops structure for multi-phase clock generation with a single-loop operation. An Alexander phase detector utilizing a flip-flop based on an improved true single-phase clock (TSPC) logic with split outputs is adopted. The proposed DLL-based CDR is an optimized solution in terms of area and power for FC wireline transceivers. The recovered clock exhibits an RMS jitter of 590 fs and a peak-to-peak jitter of 3.8 ps. The circuit …