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Journal

2008

Aspect Ratio Trapping

Articles 1 - 2 of 2

Full-Text Articles in Engineering

Deep Submicron Pattern Formation For Selective Epitaxial Growth Of Ii-V Semiconductors, Kenny Fourspring Jan 2008

Deep Submicron Pattern Formation For Selective Epitaxial Growth Of Ii-V Semiconductors, Kenny Fourspring

Journal of the Microelectronic Engineering Conference

In the world of optoelectronics a common barrier has been integrating logic and device circuits on a single substrate, as it was generally only possible to optimize the device for the logic, or the optoelectronic device at hand. However, a new approach that uses metal organic chemical vapor deposition (MOCVD) enables the growth of Ill-V semiconductors on silicon substrates. The fact that 111-V semiconductors can now be integrated within the current silicon CMOS processes may allow new possibilities. An approach to investigate the feasibility of this process has been investigated. The enabler to integrate HI-V is an innovative approach called …


Process Characterization For Integration Of Esaki Diodes Into Aspect Ratio Trapping Material, Stuart A. Sieg Jan 2008

Process Characterization For Integration Of Esaki Diodes Into Aspect Ratio Trapping Material, Stuart A. Sieg

Journal of the Microelectronic Engineering Conference

A process for forming Esaki Diodes in Germanium bulk material was characterized. In doing so its processing characteristics were studied to determine whether it could be transferred into Aspect Ratio Trapping, ART, material. It was determined that transfer was feasible with the optimization of the spin on dopant process and strict control of the wet etching of the spin on dopant and Aluminum. Following process characterization electrical data was collected for a range of devices with varying process parameters. The maximum peak to valley current ratio was 1.5 and maximum peak current density was 5kA/cm2. The PVCR value …