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Articles 1 - 21 of 21
Full-Text Articles in Engineering
Evaluation Of Source Geometry Using A Pinhole Camera, Marilyn Maloney
Evaluation Of Source Geometry Using A Pinhole Camera, Marilyn Maloney
Journal of the Microelectronic Engineering Conference
A pinhole camera was used to evaluate source geometry of the GCA6700 g-line stepper. To create the camera, a photomask with various pinhole sizes was placed in the stepper, in close proximity to a wafer to generate an image. The images were evaluated to determine the shape and observe the radial intensity of the source. The variation across the source was evaluated because varying intensity across the wafer results and contributes to changes in critical dimension. Dose was varied in order to show how an illumination source might be characterized. As dose increased, the pinhole image became larger. Stacking the …
I-Line Resist Process Monitor, Joseph G. Perez
I-Line Resist Process Monitor, Joseph G. Perez
Journal of the Microelectronic Engineering Conference
In order to confidently reproduce results obtained from experimentation or standard processing, the stability of the involved equipment’s performance must be understood. Therefore, it is important to monitor, on a regular basis, the outputs of an equipment set which are delivering a desired process. In this paper, a qualification test or "qual” will be defined for RIT’s 150mm i-line photolithography process which utilizes a Canon FPA 2000-i1 exposure tool.
Development Of Automated Alignment Methodology On The Canon I-Line Stepper, Domenico Dipaola
Development Of Automated Alignment Methodology On The Canon I-Line Stepper, Domenico Dipaola
Journal of the Microelectronic Engineering Conference
Lithography is one of the most crucial processes that is used in modern integrated circuit (IC) fabrication. Level to level alignment and overlay measurements are key factors within lithographic processes. A stepper with an automated level to level alignment system can significantly improve wafer throughput and therefore increase profit for a company. There are many factors that can either enhance or hinder a tool's ability to align one level on top of another. For the past couple of years, RIT has had a Canon FPA 2000 ill-line stepper in their possession and the automated alignment system has never been utilized, …
Utilization Of The Hitachi S-6780 Sem For Critical Dimension Measurement, Timothy Footer
Utilization Of The Hitachi S-6780 Sem For Critical Dimension Measurement, Timothy Footer
Journal of the Microelectronic Engineering Conference
The necessity of being able to accurately measure sub-micron features in devices fabricated in RIT’s microelectronic manufacturing facility has resulted in the acquisition of a Hitachi S-6780 CD SEM The Hitachi SEM will remove all user error, completely automate the current CD measurement procedure, and yield more accurate results. This project entails learning the operations of this model of SEM and the creation of various instruction manuals to allow this tool to become a commonly used piece of equipment at RIT. Explained will be the different kinds of files and measurement techniques the S-6780 SEM uses. Various experiments were performed …
Optical Emission Spectroscopy For Plasma Etch Endpoint Detection, Keith R. Miller
Optical Emission Spectroscopy For Plasma Etch Endpoint Detection, Keith R. Miller
Journal of the Microelectronic Engineering Conference
Optical Emission Spectroscopy was implemented for determining the endpoint of film removal through detecting shifts in plasma emission intensity during an etch process. A preliminary procedure has been developed for detecting endpoint with the factory nitride and oxide etch processes at RIT. In conjunction with the development of an endpoint process, the minimum sensitivity for the OES endpoint system was investigated. A minimum of 0.5% exposed nitride versus resist area is required for accurately detecting endpoint on Nitride, while 5% open area is necessary for Oxide.
Cross Sectional Analysis Of Ic Devices Using Polishing Techniques And Sem Imaging, Peter G. Terrana
Cross Sectional Analysis Of Ic Devices Using Polishing Techniques And Sem Imaging, Peter G. Terrana
Journal of the Microelectronic Engineering Conference
The purpose of the project was to develop a universal procedure for obtaining a cross section of various IC devices, use a Scanning Electron Microscope (SEM) to document these devices, and identify different layers and try to obtain dimensions for the devices. The technique was developed using a mechanical polishing procedure followed by a chemical mechanical polishing step, and worked as expected, producing very good images of the cross section of various film stacks and devices. Wide ranges of devices were analyzed to test the robustness of the process. Film stacks could be measured in both thickness and composition (with …
Incorporation Of Control Charts Into A Manufacturing Execution System, Charles J. Gruener
Incorporation Of Control Charts Into A Manufacturing Execution System, Charles J. Gruener
Journal of the Microelectronic Engineering Conference
The wafer fabrication facility at RIT has a primary goal of being a teaching facility. Tracking of the student run wafer lots is accomplished very effectively by MESA, a lot-tracking software package. The system is configured to collect information, but data base queries were not set up to display this information. MESA has the option of outputting information from the databases to a statistical software package called Quality Analyst. Quality Analyst displays control charts for the extracted data, providing quick, visual interpretation of the process in question. The adaptation of this software into the RIT Microelectronic Engineering fabrication facility has …
Dry Etch Of Shadow Trench Isolation, Patrick W. Reece
Dry Etch Of Shadow Trench Isolation, Patrick W. Reece
Journal of the Microelectronic Engineering Conference
Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced local oxidation of silicon (LOCOS) as the conventional isolation technique for sub-micron devices. STI increases transistor-packing density, allowing for more functionality and speed per unit area. STI offer superior latch-up immunity, smaller channel-width encroachment and better planarity. The implementation and feasibility of STI has been examined for device fabrication at RIT previously. The process utilized was etching of shallow trenches using SF6-02 dry chemistry and trench fill by TEOS (tetraethylorthosilicate) oxide deposition. The etch chemistry used did not yield anisotropic etching and appreciable undercutting was observed. …
Cmp Process Development For Shallow Trench Isolation (Sti), Robert A. Selfridge
Cmp Process Development For Shallow Trench Isolation (Sti), Robert A. Selfridge
Journal of the Microelectronic Engineering Conference
Tool characterization and optimization was performed on a Westech Model 372 Polisher. A Rhodes ESM-U pad with a #5 groove with PSA and two slurries: a Rodel Klebosol 1501-50 silica based slurry and a proprietary cerium oxide slurry were utilized. Initial polishing of blanket thermal oxide wafers on the Westech produced %WIWNU greater than 80% using the Klebosol slurry. Following tool calibrations and modifications to machine configurations, %WIWNU dropped to approximately 5%. Characterization studies were performed for Removal Rate vs. Platen RPM and for Removal Rate vs. Down Force. An increase in removal rate was determined with an increase in …
Polysilicon-Germanium Films Fabricated By Ge Sputtering, Jose L. Medina
Polysilicon-Germanium Films Fabricated By Ge Sputtering, Jose L. Medina
Journal of the Microelectronic Engineering Conference
Poly-SixGei..x films were fabricated on 500 A of oxide by a novel process. Values for X range from 0.86 to 0.45. This novel process consists of two steps as opposed to the single step polysilicon germanium deposition methods currently used in industry. Ge was deposited by PVD and polysilicon was deposited on top of the germanium by LPCVD in a silane ambient. The films were doped P~ with boron dopant and annealed at 1,000°C for 50 minutes in a nitrogen ambient. Films with 65 and 55% Ge suffered from voids and hillocks and film discontinuity. Films with 20 and 14% …
The Effect Of Fluorine On Low Temperature Boron Activation In Ultra Shallow Junctions, Jeremy J. Kempisty
The Effect Of Fluorine On Low Temperature Boron Activation In Ultra Shallow Junctions, Jeremy J. Kempisty
Journal of the Microelectronic Engineering Conference
As CMOS device dimensions continue to shrink below 200nm, one of the major limiting factors in scaling size will become the drain and source junction depth. Using fluorine to create shallower p type junctions during ion implant is one way to decrease the junction depth. The effect of fluorine on the implant and subsequent anneal processes was studied. A low temperature annealing process was developed to decrease junction depths although sufficient dopant activation is being studied.
Development Of Cosi2 Salicide Process, Oleg A. Kirillov
Development Of Cosi2 Salicide Process, Oleg A. Kirillov
Journal of the Microelectronic Engineering Conference
As RIT is continuously scaling CMOS technology to smaller dimension, the Self-Aligned Suicide (Salicide) process needs to be developed. The silicided metalization leads to low-resistivity gates, interconnections and contacts between the metal and silicon substrate. Currently, salicide processes, such as titanium silicide (TiSi2) and cobalt suicide (CoSi2), are widely used in advanced CMOS technologies. However, only CoSi2 salicide process is scalable to deep sub-micron technology, since the resistivity of CoSi2 phase is independent of the dimensions. CoSi2 salicide process using titanium nitride (TiN) as capping film has been developed. Electrical tests were performed: …
Electrolytic Plating Of Copper, Keith M. Udut
Electrolytic Plating Of Copper, Keith M. Udut
Journal of the Microelectronic Engineering Conference
ReynoldsTech graciously donated a copperelectroplating tool to R.I.T., which speaks volumes and has far reaching potentials and challenges for, innovative research, patents and, incorporation of the damascene process into the thin film labs. Upon eventual integration into the classroom environment further designed experiments, process improvement and senior design projects, electroplating will eventually replace the existing aluminum metal layers with copper for the advanced 1.0 μm and O.5μm CMOS process currently used in the R.I.T. integrated circuit processing student run factory. From a ground zero approach with safety issues in mind the ramping up of this new tool had to be …
Carbon Nanotubes: Cvd Reactor Deign And Growth Of Multi-Walled Carbon Nanotubes, Jun S. Hyun
Carbon Nanotubes: Cvd Reactor Deign And Growth Of Multi-Walled Carbon Nanotubes, Jun S. Hyun
Journal of the Microelectronic Engineering Conference
Carbon Nanotubes are researched to develop for new technology of transporting electrons in one dimension and have commercial potential as nanoscale transistors. Carbon Nanotubes need to be made by using chemical vapor deposition (CVD). This CVD technique is used to deposit thin film on substrates. As the gas decomposes, it frees up carbon atoms, which can recombine in the form of nanotubes. The conditions for the controlled and directed CVD growth of Nanotubes are planed being established with the use of thin film metal catalyst by using RIT’s CVD Reactor. This CVD reactor was designed and made for growing the …
Ohmic Contact Formation On N-Type 6h-Sic Using Poly-Si And Silicides, Asuka E. Nomura
Ohmic Contact Formation On N-Type 6h-Sic Using Poly-Si And Silicides, Asuka E. Nomura
Journal of the Microelectronic Engineering Conference
Silicon Carbide with its wide bandgap, high thermal conductivity, and high breakdown electric field is an attractive material to be used for applications in high power, and high temperature semiconductor devices. For such applications, it is extremely important to be able to form stable ohmic contacts. Various metals have been attempted to form ohmic contacts on SiC such as Ni, Ti, and Al. However it has been observed that these metallization schemes have degraded performance due to carbon accumulation by forming carbides at the interface. In this study, polycide (poly Si + silicide) based metallizations have been investigated, using NiSi …
Fabrication And Characterization Of 6h-Sic Photovoltaic Devices, Russell P. Ott
Fabrication And Characterization Of 6h-Sic Photovoltaic Devices, Russell P. Ott
Journal of the Microelectronic Engineering Conference
Silicon Carbide (SIC) photovoltaic (PV) devices have caught the interest for extra terrestrial endeavors. This is due to the excellent resistance to radiation, good thermal conductivity, and high quantum efficiency of such devices. Also the large band gap (of 2.9eV) makes it ideal for gathering high-energy UV photons thus creating a large power density. Using 1cm2 6H-SiC diode samples, photovoltaic cells were produced. Both P-on-N and Non- P were examined for this study. There are two samples for each type with varying doping concentrations. For the n-side of each sample, a multilayer of TiINiIAl metals was deposited to have …
Design And Fabrication Of On-Chip Inductors, Robert K. Requa
Design And Fabrication Of On-Chip Inductors, Robert K. Requa
Journal of the Microelectronic Engineering Conference
An inductor is a conductor arranged in an appropriate shape (such as a conducting wire wound as a coil) to supply a certain amount of self-inductance. This passive device stores magnetic energy. Simple spiral planar inductors of varying geometry were designed and fabricated on a silicon substrate insolated by silicon oxide. The process chosen for fabrication of the devices was the copper damascene process. Line widths and spaces varied from 5μm to 20μm. Thickness of the copper wire was approximately 1.5 μm. The inductors were isolated from the silicon substrate by 0.5 μm of Si02 and wires were insolated …
Full-Wafer Dmos Fabrication At Rit, Stephen Sudirgo, Alex Pamatat
Full-Wafer Dmos Fabrication At Rit, Stephen Sudirgo, Alex Pamatat
Journal of the Microelectronic Engineering Conference
A well understanding of basic structure of Double Diffused Metal Oxide Semiconductor (DMOS) and the concept of segmented large capacitor creates possibility to produce a full-wafer DMOS. Using the Mylar Mask Technology, the final metal layer can be patterned accordingly so that to leave out any damaged fragments. Thus, it will increase the possibility of higher yield. Most of the basic fabrication processes will be done at RIT microelectronics lab facilities, and the functionality tests will be conducted at Naval Research Lab. Therefore, this paper is intended to give a general overview of concepts involved and the fabrication processes.
Reflection Transmission Modulator, Ti'ona I. Mccauley
Reflection Transmission Modulator, Ti'ona I. Mccauley
Journal of the Microelectronic Engineering Conference
Microelectromechanical systems (MEMS) have gained increasing importance in the semiconductor industry. The research done had three main goals. The first was to pattern a corrugated pattern in photoresist. The second was to obtain a variation in the stress of the materials used and the third was to fabricate a micro. The micro shutter is constructed using a stack consisting of Amorphous Carbon and Aluminum and is anchored at one end to the substrate. In this study two of the three goals were met however there were some difficulties with the fabrication of the micro shutter that will be discussed later …
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Journal of the Microelectronic Engineering Conference
Traditionally, microelectromechanical systems (MEMS) have been fabricated using standard surface micromachining or bulk micromachining processes with prior or subsequent CMOS incorporation. Recently, a new hybrid technique known as CMOS enicromachining has been developed allowing for parallel fabrication of mechanical and electrical components. A single axis and dual axis accelerometer have been designed for submission for an ASIMPS alpha run using the CMOS micromachining process. Electrical and mechanical analysis and simulations for the single axis accelerometer have been performed. The sensitivity of the single axis accelerometer has been calculated to be 19.66mV/g neglecting the effects of parasitic capacitance. The released die …
Characterization Of Su-8 5 For Mems Applications, Sean Corcoran
Characterization Of Su-8 5 For Mems Applications, Sean Corcoran
Journal of the Microelectronic Engineering Conference
SIJ-8 is a negative photoresist that is mainly used for MEMS technology. It is currently being used l~r micro-machined gears, accelerometers, and host of other MEMS structures. In these types of MEMS devices it is important to get an image with nearly vertical sidewall angles. For example with a micromachined gear, the gear would slip easily if the gears sidewall angle not near vertical. The focus of this project was to model the sidewall angle through a designed experiment and an ANOVA was run on the data using a computer program. Also, using a linear regression analysis the functionality of …