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Experimental Study Of Fault Cones And Fault Aliasing, Vedanth Bilagi
Experimental Study Of Fault Cones And Fault Aliasing, Vedanth Bilagi
Dissertations and Theses
The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response is estimated by fault tolerant technique. The purpose …
A Fault-Tolerant Alternative To Lockstep Triple Modular Redundancy, Andrew Lockett Baldwin
A Fault-Tolerant Alternative To Lockstep Triple Modular Redundancy, Andrew Lockett Baldwin
Dissertations and Theses
Semiconductor manufacturing defects adversely affect yield and reliability. Manufacturers expend vast resources to reduce defects within their processes. As the minimum feature size get smaller, defects become increasingly difficult to prevent. Defects can change the behavior of a logic circuit resulting in a fault. Manufacturers and designers may improve yield, reliability, and profitability by using design techniques that make products robust even in the presence of faults. Triple modular redundancy (TMR) is a fault tolerant technique commonly used to mask faults using voting outcomes from three processing elements (PE). TMR is effective at masking errors as long as no more …