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Full-Text Articles in Engineering

Parallel Recording Of Neurotransmitters Release From Chromaffin Cells Using A 10 X 10 Cmos Ic Potentiostat Array With On-Chip Working Electrodes, Brian Kim, Adam Herbst, Sung Kim, Bradley Minch, Manfred Lindau Feb 2013

Parallel Recording Of Neurotransmitters Release From Chromaffin Cells Using A 10 X 10 Cmos Ic Potentiostat Array With On-Chip Working Electrodes, Brian Kim, Adam Herbst, Sung Kim, Bradley Minch, Manfred Lindau

Bradley Minch

Neurotransmitter release is modulated by many drugs and molecular manipulations. We present an active CMOS-based electrochemical biosensor array with high throughput capability (100 electrodes) for on-chip amperometric measurement of neurotransmitter release. The high-throughput of the biosensor array will accelerate the data collection needed to determine statistical significance of changes produced under varying conditions, from several weeks to a few hours. The biosensor is designed and fabricated using a combination of CMOS integrated circuit (IC) technology and a photolithography process to incorporate platinum working electrodes on-chip. We demonstrate the operation of an electrode array with integrated high-gain potentiostats and output time-division …


A Simple Low-Voltage Cascode Current Mirror With Enhanced Dynamic Performance, Bradley Minch Oct 2012

A Simple Low-Voltage Cascode Current Mirror With Enhanced Dynamic Performance, Bradley Minch

Bradley Minch

In this paper, we present a simple low-voltage MOS cascode current mirror featuring a step response and an output voltage swing comparable to those of a simple mirror and and output resistance comparable to that of a stacked mirror. The proposed mirror operates with an input voltage of Vdiode+VDSsat and can operate on a minimum supply of Vdiode + 2VDSsat. We validate the proposed mirror with a combination of simulated and measured results from a circuit prototyped from transistor arrays fabricated in a 0.5-μm CMOS process through MOSIS.


Floating-Gate Devices: They Are Not Just For Digital Memories Anymore, Paul Hasler, Bradley Minch, Chris Diorio Jul 2012

Floating-Gate Devices: They Are Not Just For Digital Memories Anymore, Paul Hasler, Bradley Minch, Chris Diorio

Bradley Minch

Since the first reported floating-gate structure in 1967, floating-gate transistors have been used widely to store digital information for long periods in structures such as EPROMs and EEPROMs. Recently floating-gate devices have found applications as analog memories, analog and digital circuit elements, and adaptive processing elements. Floating-gate devices have found commerical applications, e.g. ISD, for long-term non-volatile information storage devices for analog applications. The focus of floating-gate devices has been towards fabrication in standard CMOS processes, as opposed to the specialized processes for fabricating digital non-volatile memories. Floating-gate circuits can be designed at any or all of three levels: analog …


Synthesis Of Multiple-Input Translinear Element Networks, Bradley Minch, Paul Hasler, Chris Diorio Jul 2012

Synthesis Of Multiple-Input Translinear Element Networks, Bradley Minch, Paul Hasler, Chris Diorio

Bradley Minch

We describe two systematic procedures for synthesizing multiple-input translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each ofthese procedures with an example.


A Floating-Gate Technology For Digital Cmos Processes, Bradley Minch, Paul Hasler Jul 2012

A Floating-Gate Technology For Digital Cmos Processes, Bradley Minch, Paul Hasler

Bradley Minch

We discuss the possibility of developing high-quality floating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental procedures to address this issue and find acceptable floating-gate circuit behaviour with MOS capacitors. First, we simultaneously characterize an MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a finite, but usable range. Second, we characterize two typical floating-gateMOS circuit primitives, a floating-gate amplifier and a multiple-input …


Adaptive Circuits Using Pfet Floating-Gate Devices, Paul Hasler, Bradley Minch, Chris Diorio Jul 2012

Adaptive Circuits Using Pfet Floating-Gate Devices, Paul Hasler, Bradley Minch, Chris Diorio

Bradley Minch

In this paper, we describe our floating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add floating-gate charge by electron tunneling, and we remove floating-gate charge by hot-electron injection. With this floating-gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using …


An Autozeroing Floating-Gate Amplifier, Paul Hasler, Bradley Minch, Chris Diorio Jul 2012

An Autozeroing Floating-Gate Amplifier, Paul Hasler, Bradley Minch, Chris Diorio

Bradley Minch

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and …


Optimal Synthesis Of Mite Translinear Loops, Shyam Subramanian, David Anderson, Paul Hasler, Bradley Minch Jul 2012

Optimal Synthesis Of Mite Translinear Loops, Shyam Subramanian, David Anderson, Paul Hasler, Bradley Minch

Bradley Minch

A procedure for synthesizing multiple-input translinear element (MITE) networks that implement a given system of translinear-loop equations (STLE) is presented. The minimum number of MITEs required for implementing the STLE, which is equal to the number of current variables in the STLE, is attained. The number of input gates ofthe MITEs is minimal amongst those MITE networks that satisfy the STLE and have the minimum number of MITEs. The synthesized MITE networks have a unique operating point and, in many cases, the network is guaranteed to be stable in a particular sense. This synthesis procedure exploits the relationship between MITEproduct-of-power-law …


Multiple-Input Translinear Element Networks, Bradley Minch, Paul Hasler, Chris Diorio Jul 2012

Multiple-Input Translinear Element Networks, Bradley Minch, Paul Hasler, Chris Diorio

Bradley Minch

We describe a new class of translinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call such circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element, which we defined recently that produces an output current that is exponential in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and provide a systematic matrix technique for analyzing the nonlinear relationships implemented by any given circuit. We also show experimental data from three MITE networks that were fabricated in a 1.2-μm double-poly CMOS process.


Synthesis Of Translinear Analog Signal Processing Systems, Eric Mcdonald, Bradley Minch Jul 2012

Synthesis Of Translinear Analog Signal Processing Systems, Eric Mcdonald, Bradley Minch

Bradley Minch

In this paper, we describe a structured methodology for synthesizing translinear analog signal-processing systems from high-level descriptions in the time domain. The circuits are implemented from elements called multiple-input translinear elements (MITEs). We illustrate the synthesis methodology with the simple example ofan RMS-DC converter.


Programmable Multiple Input Translinear Elements, Haw-Jing Jo, Guillermo Serrano, Paul Hasler, David Anderson, Bradley Minch Jul 2012

Programmable Multiple Input Translinear Elements, Haw-Jing Jo, Guillermo Serrano, Paul Hasler, David Anderson, Bradley Minch

Bradley Minch

Large networks composed of multiple input translinear elements (MITEs) have been typically limited by the mismatches between individual MITEs. This paper presents the methodology that allows for such systems to be feasible through the application of floating-gate programming techniques. We introduce designs for a programmable MITE, and demonstrate the ability to systematically reduce offsets through accurate programming of example circuits.


Synthesis Of Static And Dynamic Multiple-Input Translinear Element Networks, Bradley Minch Jul 2012

Synthesis Of Static And Dynamic Multiple-Input Translinear Element Networks, Bradley Minch

Bradley Minch

In this paper, we discuss the process of synthesizing static and dynamic multiple-input translinear element (MITE) networks systematically from high-level descriptions given in the time domain, in terms of static polynomial constraints and algebraic differential equations. We provide several examples, illustrating the process for both static and dynamic system constraints. Although our examples will all involve MITE networks, the early steps of the synthesis process are equally applicable to the synthesis of static and dynamic translinear-loop circuits.


Integration Of Chemical Sensing And Electrowetting Actuation On Chemoreceptive Neuron Mos (Cνmos) Transistors, Nick Shen, Zengtao Liu, Blake Jacquot, Bradley Minch, Edwin Kan Jul 2012

Integration Of Chemical Sensing And Electrowetting Actuation On Chemoreceptive Neuron Mos (Cνmos) Transistors, Nick Shen, Zengtao Liu, Blake Jacquot, Bradley Minch, Edwin Kan

Bradley Minch

An integration of chemical sensors and electrowetting actuators based on the chemoreceptive neuron MOS (CνMOS) transistors has brought forth a novel system-on-chip approach to the microfluidic system. The extended floating-gate structure of the CνMOS transistors enables monolithic sensing and actuating schemes. The sensors with generic chemical receptive areas have been characterized with various fluids, and have demonstrated a high sensitivity from the current differentiation and a large dynamic range from threshold-voltage shifts in sensing polar and electrolytic liquids. The actuators have illustrated valve functions based on contact-angle modification by nonvolatile charge injection into the channel wall. Electrochemical models for sensing …


A Low-Voltage Mos Cascode Current Mirror For All Current Levels, Bradley Minch Jul 2012

A Low-Voltage Mos Cascode Current Mirror For All Current Levels, Bradley Minch

Bradley Minch

In this paper, we describe a simple low-voltage MOS cascode current mirror that functions well at all current levels, ranging from weak inversion to strong inversion. The circuit features a wide output voltage swing and requires an input voltage of approximately one diode drop plus a saturation voltage. We present experimental results from a version of the current mirror that was fabricated in a 0.5 μm CMOS process along with a comparison with several other current mirrors with respect both to required input voltage and to output compliance voltage.


A Fully Programmable Log-Domain Bandpass Filter Using Multiple-Input Translinear Elements, Ravi Chawla, Haw-Jing Lo, Arindam Basu, Paul Hasler, Bradley Minch Jul 2012

A Fully Programmable Log-Domain Bandpass Filter Using Multiple-Input Translinear Elements, Ravi Chawla, Haw-Jing Lo, Arindam Basu, Paul Hasler, Bradley Minch

Bradley Minch

In this paper a second order log-domain bandpass filter using multiple input translinear elements (MITEs) operating at a 3V supply. We enhance the capabilities of the filter by utilizing programmable MITE structures as well as programmable current sources, which are covered in this paper. The synthesized bandpass filter is implemented and fabricated using these programmable translinear devices (MITEs). Experimental results are shown from circuit fabricated on a 0.5μm nwell CMOS process available through MOSIS.


Synthesis Of Dynamic Multiple-Input Translinear Element Networks, Bradley Minch Jul 2012

Synthesis Of Dynamic Multiple-Input Translinear Element Networks, Bradley Minch

Bradley Minch

In this paper, the author discusses an approach to the synthesis of dynamic translinear circuits built from multiple-input translation elements (MITEs). In this method, we realize separately the basic static nonlinearities and dynamic signal-processing functions that when cascaded together, form the system that one wishes to construct. The circuit is then simplified systematically through local transformations that do not alter the behavior of the system. The author illustrates the method by synthesizing a simple nonlinear dynamical system, an RMS-DC converter.


Adaptive Translinear Analog Signal Processing: A Prospectus, Eric Mcdonald, Kofi Odame, Bradley Minch Jul 2012

Adaptive Translinear Analog Signal Processing: A Prospectus, Eric Mcdonald, Kofi Odame, Bradley Minch

Bradley Minch

We have devised a systematic method of transforming high-level time-domain descriptions of linear and nonlinear adaptive signal-processing algorithms into compact, continuous-time analog circuitry using basic units called multiple-input translinear elements (MITEs). In this paper, we describe the current state of the art and illustrate the method with an example of an analog phase-locked loop (PLL).


Synthesis Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch Jul 2012

Synthesis Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch

Bradley Minch

In this paper, we present a methodology for synthesizing analog systems using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing part of a Least-Mean-Squares (LMS) adaptation algorithm used in an analog adaptive filter. We present preliminary experimental results from a chip fabricated ina 0.5-μm double-poly CMOS process.


Inverting The Bipolar Differential Pair For Low-Voltage Applications, Bradley Minch Jul 2012

Inverting The Bipolar Differential Pair For Low-Voltage Applications, Bradley Minch

Bradley Minch

In this paper, the author presents a new bipolar differential transconductor that functions just like an emitter-degenerated differential pair, except for the following: it operates on a low power supply; it has a rail-to-rail common-mode input-voltage range; permits a wide output-voltage swing; has a transconductance gain that is nearly constant with the common-mode input voltage; and requires only n-p-n transistors in the signal path. We describe intuitively how the circuit functions and provide DC measurements from a prototype circuit, breadboarded from a quad TPQ3904 and a thick-film resistor array demonstrating proper operation on a single-ended 1.2-V power supply.


Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch Jul 2012

Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch

Bradley Minch

In this paper, we propose a modification to the class of circuits known as multiple input translinear element (MITE) networks. Our proposed modification leads to a MITE network that is free from certain nonidealities encountered in previous implementations. Further, the new MITE network described here readily accommodates the use of bipolar junction transistors in the input and output stages, thus implying a significantly wider dynamic range than we can achieve using subthreshold MOSFETs.


Synthesis Of Multiple-Input Translinear Element Log-Domain Filters, Bradley Minch Jul 2012

Synthesis Of Multiple-Input Translinear Element Log-Domain Filters, Bradley Minch

Bradley Minch

I present a simple procedure for synthesizing multiple-input translinear element (MITE) log-domain filters from state-space descriptions. We can obtain such state-space descriptions from a variety of sources, and the procedure that I describe can be utilized regardless of the source of the description. We can often derive such descriptions conveniently from already extant filters that have been previously implemented using a different class of filters. I shall illustrate the synthesis procedure by deriving two simple MITE log-domain filters from single-ended voltage-mode OTA-C filter prototypes-I synthesize both a first-order lowpass filter and a fully tunable second-order lowpass filter.


A Second-Order Section Built From Autozeroing Floating-Gate Amplifiers, Paul Hasler, Theron Stanford, Bradley Minch Jul 2012

A Second-Order Section Built From Autozeroing Floating-Gate Amplifiers, Paul Hasler, Theron Stanford, Bradley Minch

Bradley Minch

We introduce the autozeroing floating-gate (AFGA) secondorder section. We built this second-order filter where the corner frequency and Q are electronically tunable based on a classic filter topology and principles of operational transconductance amplifiers. We built this second order filter using three AFGAs—our floating-gate amplifier that sets its operating point by the interaction of hot-electron injection and electron tunneling.


A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch Jul 2012

A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch

Bradley Minch

In this paper, the author describes a simple low-voltage MOS cascode bias circuit that functions well at all current levels, ranging from weak inversion to strong inversion. He describes an approach to defining the onset of saturation that is generally useful from a bias-circuit design viewpoint and explains specifically how it was used in designing the low-voltage cascode bias circuit. The author discusses an efficient strategy for laying out the cell in the full-stacked style. He also presents experimental results from a version of the bias circuit that was fabricated in a 1.2-μm CMOS process.


Multi-Level Simulation Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch Jul 2012

Multi-Level Simulation Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch

Bradley Minch

In this paper, we briefly discuss a methodology for synthesizing analog systems from a high-level behavioral specification using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing a Least-Mean-Square (LMS) adaptation algorithm used in an analog adaptive filter. The resulting systems can be simulated at various levels of abstraction during the design phase. As an example, we presentsimulation results from a four-tap analog adaptive filter simulated using Matlab and SPICE.


Analog Vlsi Implementation Of Support Vector Machine Learning And Classification, Sheng-Yu Peng, Bradley Minch, Paul Hasler Jul 2012

Analog Vlsi Implementation Of Support Vector Machine Learning And Classification, Sheng-Yu Peng, Bradley Minch, Paul Hasler

Bradley Minch

We propose an analog VLSI approach to implementing the projection neural networks adapted for the supportvector machine with radial-basis kernel functions, which are realized by a proposed floating-gate bump circuit with the adjustable width. Other proposed circuits include simple current mirrors and log-domain Alters. Neither resistors nor amplifiers are employed. Therefore it is suitable for large-scale neural network implementations. We show the measurement results of the bump circuit and verify the resulting analog signal processing system on the transistor level by using a SPICE simulator. The same approach can also be applied to the support vectorregression. With these analog signal …


A Long-Channel Model For The Asymmetric Double-Gate Mosfet Valid In All Regions Of Operation, Abhishek Kammula, Bradley Minch Jul 2012

A Long-Channel Model For The Asymmetric Double-Gate Mosfet Valid In All Regions Of Operation, Abhishek Kammula, Bradley Minch

Bradley Minch

We present a physically based, continuous analytical model for long-channel double-gate MOSFETs. The model is particularly well suited for implementation in circuit simulators due to the simple expressions for the current andthe continuous nature of the derivatives of the current which improves convergence behavior.


A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch Jul 2012

A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch

Bradley Minch

The author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, …


A Transistor-Only Circuit Model Of The Autozeroing Floating-Gate Amplifier, Paul Hasler, Matt Kucic, Bradley Minch Jul 2012

A Transistor-Only Circuit Model Of The Autozeroing Floating-Gate Amplifier, Paul Hasler, Matt Kucic, Bradley Minch

Bradley Minch

We developed an transistor-only version of our autozeroing floating-gate amplifier (AFGA). We use a subthreshold transistor to model the behavior of an electron-tunneling device, and we use another subthreshold transistor to model the behavior of pFET hot-electron injection. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data. This circuit is a bandpass filter, and behaves similarly to the AFGA with different operating parameters. Both the low-frequency and high-frequency cutoffs are controlled electronically, as is done in continuous-time filters. This circuit has a low-frequency cutoff at frequencies above 1 Hz, and …


A Simple Way To Extend The Common-Mode Input-Voltage Range Of The Mos Differential Pair, Bradley Minch Jul 2012

A Simple Way To Extend The Common-Mode Input-Voltage Range Of The Mos Differential Pair, Bradley Minch

Bradley Minch

In this paper, we describe a simple technique involving indirect negative feedback that extends the useable common-mode input-voltage range of the MOS differential pair by a saturation voltage. In this method, we use a replica differential pair to sense when the bias transistor supplying the tail current falls out of saturation. We then set the bias voltage so that the sum of the two differential-pair output currents is equal to the bias current. We present experimental results from a version of the differential pair that was fabricated in a 0.5 μm CMOS process along with a comparison with an identical …


Hysteretic Threshold Logic And Quasi-Delay Insensitive Asynchronous Design, Mark Neidengard, Bradley Minch Jul 2012

Hysteretic Threshold Logic And Quasi-Delay Insensitive Asynchronous Design, Mark Neidengard, Bradley Minch

Bradley Minch

We introduce the class of hysteretic linear-threshold (HLT) logic functions as a novel extension of linear threshold logic, and prove their general applicability for constructing state-holding Boolean functions. We then demonstrate a fusion of HLT logic with the quasi-delay insensitive style of asynchronous circuit design, complete with logical design examples. Future research directions are also identified.