Open Access. Powered by Scholars. Published by Universities.®
- Keyword
-
- Hardware Security (2)
- Machine Learning (2)
- Performance Counters (2)
- Process Variations (2)
- Reliability (2)
-
- CMOS Active Pixel Sensor (1)
- CMOS imager (1)
- Error Correction (1)
- FPGAs (1)
- Fluorescence lifetime (1)
- Heterogeneous Processor (1)
- Localized hotspots (1)
- Noise (1)
- PUFs (1)
- Performance/Watt (1)
- Physical Unclonable Function (1)
- Physical Unclonable Functions (1)
- Physically Unclonable Functions (1)
- Reconfiguration (1)
- Reliability Estimation (1)
- Temperature Estimation (1)
- Temperature Monitoring (1)
- Thread Scheduling (1)
- Time-domain Fluorimeter (1)
- VLSI (1)
- Variation Aware (1)
- Publication
Articles 1 - 6 of 6
Full-Text Articles in Engineering
Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu
Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu
Doctoral Dissertations
A basic premise behind modern secure computation is the demand for lightweight cryptographic primitives, like identifier or key generator. From a circuit perspective, the development of cryptographic modules has also been driven by the aggressive scalability of complementary metal-oxide-semiconductor (CMOS) technology. While advancing into nano-meter regime, one significant characteristic of today's CMOS design is the random nature of process variability, which limits the nominal circuit design. With the continuous scaling of CMOS technology, instead of mitigating the physical variability, leveraging such properties becomes a promising way. One of the famous products adhering to this double-edged sword philosophy is the Physically …
Dynamic Processor Reconfiguration For Power, Performance And Reliability Management, Sudarshan Srinivasan
Dynamic Processor Reconfiguration For Power, Performance And Reliability Management, Sudarshan Srinivasan
Doctoral Dissertations
Technology advancements allowed more transistors to be packed in a smaller area, while the improved performance helped in achieving higher clock frequencies. This, unfortunately led to a power density problem, forcing processor industry to lower the clock frequency and integrate multiple cores on the same die. Depending on core characteristics, the multiple cores in the die could be symmetric or asymmetric. Asymmetric multi-core processors (AMPs) have been proposed as an alternative to symmetric multi-cores to improve power efficiency. AMPs comprise of cores that implement the same ISA, but differ in performance and power characteristics due to varying sizes of micro-architectural …
On Physical Disorder Based Hardware Security Primitives, Arunkumar Vijayakumar
On Physical Disorder Based Hardware Security Primitives, Arunkumar Vijayakumar
Doctoral Dissertations
With CMOS scaling extending transistors to nanometer regime, process variations from manufacturing impacts modern IC design. Fortunately, such variations have enabled an emerging hardware security primitive - Physically Unclonable Function. Physically Unclonable Functions (PUFs) are hardware primitives which utilize disorder from manufacturing variations for their core functionality. In contrast to insecure non-volatile key based roots-of-trust, PUFs promise a favorable feature - no attacker, not even the PUF manufacturer can clone the disorder and any attempt at invasive attack will upset that disorder. Despite a decade of research, certain practical problems impede the widespread adoption of PUFs. This dissertation addresses the …
Variation Aware Placement For Efficient Key Generation Using Physically Unclonable Functions In Reconfigurable Systems, Shrikant S. Vyas
Variation Aware Placement For Efficient Key Generation Using Physically Unclonable Functions In Reconfigurable Systems, Shrikant S. Vyas
Masters Theses
With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by FPGA-based encrypt/decrypt cores secured with secret keys. Physical unclonable functions (PUFs) use random manufacturing variations to generate outputs that can be used in keys. These outputs are specific to a chip and can be used to create device-tied secret keys. Due to reliability issues with PUFs, key generation with PUFs typically requires error correction techniques. This can result in substantial hardware costs. Thus, the total cost of a $n$-bit key far exceeds just the cost of …
Development Of A Portable Cmos Time-Domain Fluorescence Lifetime Imager, Hongtao Wang
Development Of A Portable Cmos Time-Domain Fluorescence Lifetime Imager, Hongtao Wang
Doctoral Dissertations
Modern laboratory equipments to measure the excited-state lifetime of fluorophores usually include an expensive picosecond pulsed-laser excitation source, a fragile photomultiplier tube, and a large instrument body for optics. A portable and robust device to make fluorescence lifetime measurement in nanosecond scale is of great attraction for chemists and biologists. This dissertation reports the development of a portable LED time-domain fluorimeter from an all-solid-state discrete-component prototype to its advanced CMOS integrated circuit implementation. The motivation of the research is to develop a multiplexed fluorimeter for point-of-care diagnosis. Instruments developed by this novel method have higher fill factor, are more portable, …
Processor Temperature And Reliability Estimation Using Activity Counters, Mayank Chhablani
Processor Temperature And Reliability Estimation Using Activity Counters, Mayank Chhablani
Masters Theses
With the advent of technology scaling lifetime reliability is an emerging threat in high-performance and deadline-critical systems. High on-chip thermal gradients accelerates localised thermal elevations (hotspots) which increases the aging rate of the semiconductor devices. As a result, reliable operation of the processors has become a challenging task. Therefore, cost effective schemes for estimating temperature and reliability are crucial. In this work we present a reliability estimation scheme that is based on a light-weight temperature estimation technique that monitors hardware events. Unlike previously pro- posed hardware counter-based approaches, our approach involves a linear-temporal-feedback estimator, taking into account the effects of …