Engineering Commons^™

Protecting Return Address Integrity For Risc-V Via Pointer Authentication, Yuhe Zhao

Masters Theses

Embedded systems based on lightweight microprocessors are becoming more prevalent in various applications. However, the security of them remains a significant challenge due to the limited resources and exposure to external threats. Especially, some of these devices store sensitive data and control critical devices, making them high-value targets for attackers. Software security is particularly important because attackers can easily access these devices on the internet and obtain control of them by injecting malware.

Return address (RA) hijacking is a common software attack technique used to compromise control flow integrity (CFI) by manipulating memory, such as return-to-libc attacks. Several methods have …

Incorporating Machine Learning With Satellite Data To Support Critical Infrastructure Measurement And Sustainable Development, Aggrey Muhebwa

Doctoral Dissertations

Under the umbrella concept of Artificial Intelligence (AI) for good, recent advances in machine learning and large-scale data analysis have opened new opportunities to solve humanity’s most pressing challenges. Improvements in computation complexity and advances in AI (e.g., Vision Transformers) have led to faster and more effective techniques for extracting high-dimensional patterns from large-scale heterogeneous datasets (big data). Further, as satellite data become increasingly available at varying temporal-spatial resolutions, AI tools are helping us to better understand the underlying causes of environmental and socioeconomic changes at an unprecedented scale, ushering in an era of data-driven decision-making to support sustainable and …

Fingerprinting For Chiplet Architectures Using Power Distribution Network Transients, Matthew G. Burke

Masters Theses

Chiplets have become an increasingly popular technology for extending Moore's Law and improving the reliability of integrated circuits. They do this by placing several small, interacting chips on an interposer rather than the traditional, single chip used for a device. Like any other type of integrated circuit, chiplets are in need of a physical layer of security to defend against hardware Trojans, counterfeiting, probing, and other methods of tampering and physical attacks.

Power distribution networks are ubiquitous across chiplet and monolithic ICs, and are essential to the function of the device. Thus, we propose a method of fingerprinting transient signals …

Security Of Hardware Accelerators In Multi-Tenant Fpga Environments, Shayan Moini

Doctoral Dissertations

Field-programmable gate arrays (FPGAs) play an important role in the acceleration of computationally expensive algorithms for machine learning, aerospace, and ASIC prototyping. The emergence of FPGAs in the cloud (cloud FPGAs) has accelerated FPGA adoption in various applications due to their low initial cost and the ability to quickly prototype a design. Multi-tenancy, in which multiple users execute circuitry in the same FPGAs simultaneously with logical isolation, reduces cloud FPGA usage cost and increases FPGA utilization. Multi-tenancy introduces new security challenges, such as remote side-channel and fault injection attacks, that cannot be addressed with traditional countermeasures against attacks. In this …

Formally Verifiable Synthesis Flow In Fpgas, Anurag V. Muttur

Masters Theses

FPGAs are used in a wide variety of digital systems. Due to their ability to support parallelism and specialization, these devices are becoming more commonplace in fields such as machine learning. One of the biggest benefits of FPGAs, logic specialization, can lead to security risks. Prior research has shown that a large variety of malicious circuits can snoop on sensitive user data, induce circuit faults, or physically damage the FPGA. These Trojan circuits can easily be crafted and embedded in FPGA designs. Often, these Trojans are small, consume little power in comparison to the target circuit, and are hard to …

Integration Of Digital Signal Processing Block In Symbiflow Fpga Toolchain For Artix-7 Devices, Andrew T. Hartnett

Masters Theses

The open-source community is a valuable resource for many hobbyists and researchers interested in collaborating and contributing towards publicly available tools. In the area of field programmable gate arrays (FPGAs) this is no exception. Contributors seek to reverse-engineer the functions of large proprietary FPGA devices. An interesting challenge for open-source FPGA engineers has been reverse-engineering the operation and bitstreams of digital signal processing (DSP) blocks located in FPGAs. SymbiFlow is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. For SymbiFlow, mapping logical multipliers to DSP blocks and generating DSP block bitstreams …

On Improving Robustness Of Hardware Security Primitives And Resistance To Reverse Engineering Attacks, Vinay C. Patil

Doctoral Dissertations

The continued growth of information technology (IT) industry and proliferation of interconnected devices has aggravated the problem of ensuring security and necessitated the need for novel, robust solutions. Physically unclonable functions (PUFs) have emerged as promising secure hardware primitives that can utilize the disorder introduced during manufacturing process to generate unique keys. They can be utilized as \textit{lightweight} roots-of-trust for use in authentication and key generation systems. Unlike insecure non-volatile memory (NVM) based key storage systems, PUFs provide an advantage -- no party, including the manufacturer, should be able to replicate the physical disorder and thus, effectively clone the PUF. …

Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas, Georgios Provelengios

Doctoral Dissertations

Embedded systems and field-programmable gate arrays (FPGAs) have become crucial parts of the infrastructure that supports our modern technological world. Given the multitude of threats that are present, the need for secure computing systems is undeniably greater than ever. Embedded systems and FPGAs are governed by characteristics that create unique security challenges and vulnerabilities. Despite their array of uses, embedded systems are often built with modest microprocessors that do not support the conventional security solutions used by workstations, such as virus scanners. In the first part of this dissertation, a microprocessor defense mechanism that uses a hardware monitor to protect …

Enabling Iot Authentication, Privacy And Security Via Blockchain, Md Nazmul Islam

Doctoral Dissertations

Although low-power and Internet-connected gadgets and sensors are increasingly integrated into our lives, the optimal design of these systems remains an issue. In particular, authentication, privacy, security, and performance are critical success factors. Furthermore, with emerging research areas such as autonomous cars, advanced manufacturing, smart cities, and building, usage of the Internet of Things (IoT) devices is expected to skyrocket. A single compromised node can be turned into a malicious one that brings down whole systems or causes disasters in safety-critical applications. This dissertation addresses the critical problems of (i) device management, (ii) data management, and (iii) service management in …

Formal Verification Of Divider And Square-Root Arithmetic Circuits Using Computer Algebra Methods, Atif Yasin

Doctoral Dissertations

A considerable progress has been made in recent years in verification of arithmetic circuits such as multipliers, fused multiply-adders, multiply-accumulate, and other components of arithmetic datapaths, both in integer and finite field domain. However, the verification of hardware dividers and square-root functions have received only a limited attention from the verification community, with a notable exception for theorem provers and other inductive, non-automated systems. Division, square root, and transcendental functions are all tied to the basic Intel architecture and proving correctness of such algorithms is of grave importance. Although belonging to the same iterative-subtract class of architectures, they widely differ …

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …

Analysis And Verification Of Arithmetic Circuits Using Computer Algebra Approach, Tiankai Su

Doctoral Dissertations

Despite a considerable progress in verification of random and control logic, advances in formal verification of arithmetic designs have been lagging. This can be attributed mostly to the difficulty of efficient modeling of arithmetic circuits and data paths without resorting to computationally expensive Boolean methods, such as Binary Decision Diagrams (BDDs) and Boolean Satisfiability (SAT) that require ``bit blasting'', i.e., flattening the design to a bit-level netlist. Similarly, approaches that rely on computer algebra and Satisfiability Modulo Theories (SMT) methods are either too abstract to handle the bit-level complexity of arithmetic designs or require solving computationally expensive decision or satisfiability …

Trustworthy Systems And Protocols For The Internet Of Things, Arman Pouraghily

Doctoral Dissertations

Processor-based embedded systems are integrated into many aspects of everyday life such as industrial control, automotive systems, healthcare, the Internet of Things, etc. As Moore’s law progresses, these embedded systems have moved from simple microcontrollers to full-scale embedded computing systems with multiple processor cores and operating systems support. At the same time, the security of these devices has also become a key concern. Our main focus in this work is the security and privacy of the embedded systems used in IoT systems. In the first part of this work, we take a look at the security of embedded systems from …

Design Of Hardware With Quantifiable Security Against Reverse Engineering, Shahrzad Keshavarz

Doctoral Dissertations

Semiconductors are a 412 billion dollar industry and integrated circuits take on important roles in human life, from everyday use in smart-devices to critical applications like healthcare and aviation. Saving today's hardware systems from attackers can be a huge concern considering the budget spent on designing these chips and the sensitive information they may contain. In particular, after fabrication, the chip can be subject to a malicious reverse engineer that tries to invasively figure out the function of the chip or other sensitive data. Subsequent to an attack, a system can be subject to cloning, counterfeiting, or IP theft. This …

Efficient Hardware Primitives For Securing Lightweight Systems, Siva Nishok Dhanuskodi

Doctoral Dissertations

In the era of IoT and ubiquitous computing, the collection and communication of sensitive data is increasingly being handled by lightweight Integrated Circuits. Efficient hardware implementations of crytographic primitives for resource constrained applications have become critical, especially block ciphers which perform fundamental operations such as encryption, decryption, and even hashing. We study the efficiency of block ciphers under different implementation styles. For low latency applications that use unrolled block cipher implementations, we design a glitch filter to reduce energy consumption. For lightweight applications, we design a novel architecture for the widely used AES cipher. The design eliminates inefficiencies in data …

Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li

Doctoral Dissertations

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: …

A Study On Controlling Power Supply Ramp-Up Time In Sram Pufs, Harshavardhan Ramanna

Masters Theses

With growing connectivity in the modern era, the risk of encrypted data stored in hardware being exposed to third-party adversaries is higher than ever. The security of encrypted data depends on the secrecy of the stored key. Conventional methods of storing keys in Non-Volatile Memory have been shown to be susceptible to physical attacks. Physically Unclonable Functions provide a unique alternative to conventional key storage. SRAM PUFs utilize inherent process variation caused during manufacturing to derive secret keys from the power-up values of SRAM memory cells.

This thesis analyzes the effect of supply ramp-up times on the reliability of SRAM …

Cmos Compatible Memristor Networks For Brain-Inspired Computing, Can Li

Doctoral Dissertations

In the past decades, the computing capability has shown an exponential growth trend, which is observed as Moore’s law. However, this growth speed is slowing down in recent years mostly because the down-scaled size of transistors is approaching their physical limit. On the other hand, recent advances in software, especially in big data analysis and artificial intelligence, call for a break-through in computing hardware. The memristor, or the resistive switching device, is believed to be a potential building block of the future generation of integrated circuits. The underlying mechanism of this device is different from that of complementary metal-oxide-semiconductor (CMOS) …

On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil

Masters Theses

Innovations in Field Programmable Gate Array (FPGA) manufacturing processes and architectural design have led to the development of extremely large FPGAs. There has also been a widespread adaptation of these large FPGAs in cloud infrastructures and data centers to accelerate search and machine learning applications. Two important topics related to FPGAs are addressed in this work: on-chip communication and security. On-chip communication is quickly becoming a bottleneck in to- day’s large multi-million gate FPGAs. Hard Networks-on-Chip (NoC), made of fixed silicon, have been shown to provide low power, high speed, flexible on-chip communication. An iterative algorithm for routing pre-scheduled time-division-multiplexed …

Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi

Doctoral Dissertations

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is …

Analog Signal Processing Solutions And Design Of Memristor-Cmos Analog Co-Processor For Acceleration Of High-Performance Computing Applications, Nihar Athreyas

Doctoral Dissertations

Emerging applications in the field of machine vision, deep learning and scientific simulation require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet these ever-increasing demands. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. The major contribution of this work is to show that analog processing can be a viable solution to this problem. This is demonstrated in the three …

Applications Of Physical Unclonable Functions On Asics And Fpgas, Mohammad Usmani

Masters Theses

With the ever-increasing demand for security in embedded systems and wireless sensor networks, we require integrating security primitives for authentication in these devices. One such primitive is known as a Physically Unclonable Function. This entity can be used to provide security at a low cost, as the key or digital signature can be generated by dedicating a small part of the silicon die to these primitives which produces a fingerprint unique to each device. This fingerprint produced by a PUF is called its response. The response of PUFs depends upon the process variation that occurs during the manufacturing process. In …

Formal Analysis Of Arithmetic Circuits Using Computer Algebra - Verification, Abstraction And Reverse Engineering, Cunxi Yu

Doctoral Dissertations

Despite a considerable progress in verification and abstraction of random and control logic, advances in formal verification of arithmetic designs have been lagging. This can be attributed mostly to the difficulty in an efficient modeling of arithmetic circuits and datapaths without resorting to computationally expensive Boolean methods, such as Binary Decision Diagrams (BDDs) and Boolean Satisfiability (SAT), that require “bit blasting”, i.e., flattening the design to a bit-level netlist. Approaches that rely on computer algebra and Satisfiability Modulo Theories (SMT) methods are either too abstract to handle the bit-level nature of arithmetic designs or require solving computationally expensive decision or …

Energy Efficient Loop Unrolling For Low-Cost Fpgas, Naveen Kumar Dumpala

Masters Theses

Many embedded applications implement block ciphers and sorting and searching algorithms which use multiple loop iterations for computation. These applications often demand low power operation. The power consumption of designs varies with the implementation choices made by designers. The sequential implementation of loop operations consumes minimal area, but latency and clock power are high. Alternatively, loop unrolling causes high glitch power. In this work, we propose a low area overhead approach for unrolling loop iterations that exhibits reduced glitch power. A latch based glitch filter is introduced that reduces the propagation of glitches from one iteration to next. We explore …

Skynet: Memristor-Based 3d Ic For Artificial Neural Networks, Sachin Bhat

Masters Theses

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs.

This work proposes a new fine-grained 3D integrated circuit technology …

Oracle Guided Incremental Sat Solving To Reverse Engineer Camouflaged Circuits, Xiangyu Zhang

Masters Theses

This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm and apply it to the camouflaged designs.

The circuit camouflage algorithms are implemented in Python, and the Oracle- guided incremental de-camouflage algorithm is implemented in C++. During this study, I evaluate the Oracle-guided de-camouflage tool (Solver, in short) performance by de-obfuscating the ISCAS-85 combinational benchmarks, which are camouflaged by the camouflage algorithms. The results show that Solver is able to efficiently de-obfuscate the ISCAS-85 benchmarks regardless of camouflaging style, and is able to do so 10.5x …

Effective Denial Of Service Attack On Congestion Aware Adaptive Network On Chip, Vijaya Deepak Kadirvel

Masters Theses

Network-On-Chip (NoC) architecture forms the new design framework in extending single processor to multiprocessor SoC. Similar to other SoCs and systems, NoCs are also susceptible to Denial of Service (DoS) attacks which degrade the performance by limiting the availability of resources to the processing cores. The stability of NoC is maintained by employing hardware monitors to detect illegal/abnormal activity or by congestion aware arbitration to obfuscate and balance the network load. Typical DoS attack model selects a random target resource and injects multiple flooding flits to reduce its functionality. The random DoS attack will not be practically effective on congestion …

Intrinsic Functions For Securing Cmos Computation: Variability, Modeling And Noise Sensitivity, Xiaolin Xu

Doctoral Dissertations

A basic premise behind modern secure computation is the demand for lightweight cryptographic primitives, like identifier or key generator. From a circuit perspective, the development of cryptographic modules has also been driven by the aggressive scalability of complementary metal-oxide-semiconductor (CMOS) technology. While advancing into nano-meter regime, one significant characteristic of today's CMOS design is the random nature of process variability, which limits the nominal circuit design. With the continuous scaling of CMOS technology, instead of mitigating the physical variability, leveraging such properties becomes a promising way. One of the famous products adhering to this double-edged sword philosophy is the Physically …

Dynamic Processor Reconfiguration For Power, Performance And Reliability Management, Sudarshan Srinivasan

Doctoral Dissertations

Technology advancements allowed more transistors to be packed in a smaller area, while the improved performance helped in achieving higher clock frequencies. This, unfortunately led to a power density problem, forcing processor industry to lower the clock frequency and integrate multiple cores on the same die. Depending on core characteristics, the multiple cores in the die could be symmetric or asymmetric. Asymmetric multi-core processors (AMPs) have been proposed as an alternative to symmetric multi-cores to improve power efficiency. AMPs comprise of cores that implement the same ISA, but differ in performance and power characteristics due to varying sizes of micro-architectural …

On Physical Disorder Based Hardware Security Primitives, Arunkumar Vijayakumar

Doctoral Dissertations

With CMOS scaling extending transistors to nanometer regime, process variations from manufacturing impacts modern IC design. Fortunately, such variations have enabled an emerging hardware security primitive - Physically Unclonable Function. Physically Unclonable Functions (PUFs) are hardware primitives which utilize disorder from manufacturing variations for their core functionality. In contrast to insecure non-volatile key based roots-of-trust, PUFs promise a favorable feature - no attacker, not even the PUF manufacturer can clone the disorder and any attempt at invasive attack will upset that disorder. Despite a decade of research, certain practical problems impede the widespread adoption of PUFs. This dissertation addresses the …