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Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala
Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala
Theses
Optimizing computational power is critical in the age of data-intensive applications and Artificial Intelligence (AI)/Machine Learning (ML). While facing challenging bottlenecks, conventional Von-Neumann architecture with implementing such huge tasks looks seemingly impossible. Hardware Accelerators are critical in efficiently deploying these technologies and have been vastly explored in edge devices. This study explores a state-of-the-art hardware accelerator; Gemmini is studied; we leveraged the open-sourced tool. Furthermore, we developed a Hardware Accelerator in the study we compared with the Non-Von-Neumann architecture. Gemmini is renowned for efficient matrix multiplication, but configuring it for specific tasks requires manual effort and expertise. We propose implementing …
Characterization Of Low Power Hfo2 Based Switching Devices For In-Memory Computing, Aseel Zeinati
Characterization Of Low Power Hfo2 Based Switching Devices For In-Memory Computing, Aseel Zeinati
Theses
Oxide based Resistive Random Access Memory (RRAM) devices are investigated as one of the promising non-volatile memories to be used for in-memory computing that will replace the classical von Neumann architecture and reduce the power consumption. These applications required multilevel cell (MLC) characteristics that can be achieved in RRAM devices. One of the methods to achieve this analog switching behavior is by performing an optimized electrical pulse. The RRAM device structure is basically an insulator between two metals as metal-insulator-metal (MIM) structure. Where one of the primary challenges is to assign an RRAM stack with both low power consumption and …