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- Metal oxide semiconductor field-effect transistors (2)
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Articles 1 - 5 of 5
Full-Text Articles in Engineering
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Extraction Of Carrier Mobility And Interface Trap Density In Ingaas Metal Oxide Semiconductor Structures Using Gated Hall Method, Thenappan Chidambaram
Legacy Theses & Dissertations (2009 - 2024)
III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for Dit and mobility. Here we employ gated Hall method to quantify the Dit spectrum at the high-κ oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values
Optical Metrology For Directed Self-Assembly Patterning Using Mueller Matrix Spectroscopic Ellipsometry Based Scatterometry, Dhairya J. Dixit
Optical Metrology For Directed Self-Assembly Patterning Using Mueller Matrix Spectroscopic Ellipsometry Based Scatterometry, Dhairya J. Dixit
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, lower cost per transistors, and higher transistor density. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require cutting-edge metrology tools for characterization.
Two-Dimensional Chalcogenides : Material Synthesis And Nano-Device Applications, Robin Bay Jacobs-Gedrim
Two-Dimensional Chalcogenides : Material Synthesis And Nano-Device Applications, Robin Bay Jacobs-Gedrim
Legacy Theses & Dissertations (2009 - 2024)
Low-dimensional nanostructures exhibit distinct properties from their bulk counterparts. Here the synthesis of novel low-dimensional nanostructures is demonstrated using both top down and bottom up processes and their properties are investigated. Two-dimensional (2D) binary sesquichalcogenides are introduced as a viable material platform for phase change random access memory, photodetection, and the investigation of topological insulator surface states. An exponential relationship is observed between layer thickness and energy consumption during switching of 2D phase change devices, ultra-high responsivity in 2D photoresistors, and surface-rich conduction in 2D topological insulator nanoplates. Additionally, methods for the assessment of chemical purity, stoichiometry, and dimensions of …
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
Legacy Theses & Dissertations (2009 - 2024)
Simultaneous migration of planar transistors to FinFET architectures, the introduction of a plurality of materials to ensure suitable electrical characteristics, and the establishment of reliable multiple patterning lithography schemes to pattern sub-10 nm feature sizes imposes formidable challenges to current in-line dimensional metrologies. Because the shape of a FinFET channel cross-section immediately influences the electrical characteristics, the evaluation of 3D device structures requires measurement of parameters beyond traditional critical dimension (CD), including their sidewall angles, top corner rounding and footing, roughness, recesses and undercuts at single nanometer dimensions; thus, metrologies require sub-nm and approaching atomic level measurement uncertainty.
Ion Implantation In Zno : Defect Interaction And Impurity Diffusion, Faisal Yaqoob
Ion Implantation In Zno : Defect Interaction And Impurity Diffusion, Faisal Yaqoob
Legacy Theses & Dissertations (2009 - 2024)
In the first part of this research we studied the entropy changes in diffusion prefactor and its