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Full-Text Articles in Engineering
An Optimized Buffer Insertion Algorithm With Delay-Power Constraints For Vlsi Layouts, Chessda Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani
An Optimized Buffer Insertion Algorithm With Delay-Power Constraints For Vlsi Layouts, Chessda Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani
Turkish Journal of Electrical Engineering and Computer Sciences
We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI layout designs. The algorithm is designed to handle multiconstraint optimizations, namely timing performance and power dissipation. The proposed algorithm is called HRTB-LA, which stands for hybrid routing tree and buffer insertion with look-ahead. In recent VLSI designs, interconnect delay has become a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. However, the buffer itself consumes power and it has been shown that power dissipation overhead due to buffer insertions is significantly high. …
Lambda Optimization Of Constraint Violating Units In Short-Term Thermal Unit Commitment Using Modified Dynamic Programming, Logavani Kandasamy, Senthil Kumar Selvaraj
Lambda Optimization Of Constraint Violating Units In Short-Term Thermal Unit Commitment Using Modified Dynamic Programming, Logavani Kandasamy, Senthil Kumar Selvaraj
Turkish Journal of Electrical Engineering and Computer Sciences
This paper presents a new approach with a three-stage optimization algorithm for the least-cost optimal solution of the unit commitment problem. In the proposed work, the optimal schedule is obtained by optimizing the lambda operator for the states that violate the inequality constraints. The objective of the work is to minimize the fuel cost when subjected to various constraints such as load balance, minimum up/down time, ramp limit, and spinning reserve. This method of committing the units yields the least-cost solution when applied to the IEEE 10-unit systems and 7-unit Indian utility practical systems scheduled for 24 h and the …
S-Visibility Problem In Vlsi Chip Design, Marzieh Eskandari, Mahdieh Yeganeh
S-Visibility Problem In Vlsi Chip Design, Marzieh Eskandari, Mahdieh Yeganeh
Turkish Journal of Electrical Engineering and Computer Sciences
In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility …