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Full-Text Articles in Engineering
Hardware Development For The Generation Of Large-Volume High Pressure Plasma By Spatiotemporal Control Of Space Charge, Nikhil Boothpur
Hardware Development For The Generation Of Large-Volume High Pressure Plasma By Spatiotemporal Control Of Space Charge, Nikhil Boothpur
Electrical & Computer Engineering Theses & Dissertations
While generating a plasma under laboratory conditions, any attempt to scale the pressure and volume leads to instabilities due to the build-up of localized space-charge. This poses a challenge in the design of the discharge chamber, type of excitation field, and the type of gas that is used in the discharge. This work investigates a spatially and temporally varying electric field to control the formation of space-charge in large-volume (greater than 5 mm in the smallest dimension) near atmospheric pressure. The simulations show that in a space-charge dominated transport, the charged species disperse both in azimuthal and radial directions in …
Fpga-Based On-Board Geometric Calibration For Linear Ccd Array Sensors, Guoqing Zhou, Linjun Jiang, Jingjin Huang, Rongting Zhang, Dequan Liu, Xiang Zhou, Oktay Baysal
Fpga-Based On-Board Geometric Calibration For Linear Ccd Array Sensors, Guoqing Zhou, Linjun Jiang, Jingjin Huang, Rongting Zhang, Dequan Liu, Xiang Zhou, Oktay Baysal
Mechanical & Aerospace Engineering Faculty Publications
With increasing demands in real-time or near real-time remotely sensed imagery applications in such as military deployments, quick response to terrorist attacks and disaster rescue, the on-board geometric calibration problem has attracted the attention of many scientists in recent years. This paper presents an on-board geometric calibration method for linear CCD sensor arrays using FPGA chips. The proposed method mainly consists of four modules—Input Data, Coefficient Calculation, Adjustment Computation and Comparison—in which the parallel computations for building the observation equations and least squares adjustment, are implemented using FPGA chips, for which a decomposed matrix inversion method is presented. A Xilinx …