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Study Of Design Tradeoffs Of Dram And Sram Memories, Using Hspice Computer Simulation, Bageshri Kale
Study Of Design Tradeoffs Of Dram And Sram Memories, Using Hspice Computer Simulation, Bageshri Kale
Theses
Semiconductor random access memories are complex systems that can be described by performance parameters such as memory cycle time, access delays, storage capacity, bit packing density, chip area and retention time. In this thesis, tradeoffs between cycle time, chip area, and storage size as reflected by bit line capacitance (Cbl) were studied as a function of particular design variables: memory cell capacitance (Cc); CMOS flip-flop sense amplifier (SA) transistor sizes; and size of precharge (PC), and word line (WL) switches. Performance was optimized using circuit simulation software, HSPICE, to observe DRAM and SRAM waveforms. With TSMC 0.18 micron technology, minimum …
Investigation Of Nanoporous Thin-Film Alumina Templates, Biswajit Das
Investigation Of Nanoporous Thin-Film Alumina Templates, Biswajit Das
Electrical & Computer Engineering Faculty Research
This paper presents the results of a systematic study of the fabrication of thin-film alumina templates on silicon and other substrates. Such templates are of significant interest for the low-cost implementation of semiconductor and metal nanostructure arrays. In addition, thin-film alumina templates on silicon have the potential for nanostructure integration with silicon electronics. Formation of thin-film alumina templates on silicon substrates was investigated under different fabrication conditions, and the dependence of pore morphology and pore formation rate on process parameters was evaluated. In addition, process conditions for improved pore size distribution and periodicity were determined. The template/silicon interface, important for …