Engineering Commons^™

Cmos Smart Camera With Focal Plane Neighborhood-Parallel Image Processing, Joseph A. Schmitz

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A neighbhorhood-based smart camera architecture is designed and implemented in a 0.13 μm CMOS technology. Each 8 × 8 region of pixels contains a small processor with local memory, which are tiled to form a full-resolution camera. Each processor operates in parallel, enabling high-speed image processing suitable for tracking and recognition tasks. The architecture features the programming flexibility of designs us- ing chip-level and row-level processors while preserving the scalability of pixel-parallel processing elements. The neighborhood processors are implemented physically be- tween the pixel photodiodes, creating multiple design challenges that are discussed in detail.

Advisors: Sina Balkir and Michael Hoffman

Subthreshold Op Amp Design Based On The Conventional Cascode Stage, Kurtis Daniel Cahill

Theses and Dissertations

Op amps are among the most-used components in electronic design. Their performance is important and is often measured in terms of gain, bandwidth, power consumption, and chip area. Although BJT amplifiers can achieve high gains and bandwidths, they tend to consume a lot of power. CMOS amplifiers utilizing the strong inversion region alone use less power than BJT amplifiers, but generally have lower gains and bandwidths. When CMOS SPICE models were improved to accurately simulate all regions of inversion, researchers began to test the performance of amplifiers operating in the weak and moderate inversion regions. Previous work had dealt with …