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Full-Text Articles in Engineering
Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin
Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin
Faculty Publications
Sponsorship: Los Alamos National Laboratory. Field Programmable Gate Arrays (FPGAs) are an attractive solution for space system electronics. Unfortunately, FPGAs are susceptible to radiation-induced single-event upsets (SEU). As such, the FPGA Reliability Studies research group (http://reliability.ee.byu.edu) at Brigham Young University has studied ways to effectively measure the static, dynamic and persistent cross sections of an FPGA desgin; each of which are characterized in some way by how the part reacts to an SEU. One such method is to actually radiate an FPGA and monitor how it reacts to SEUs. A cheaper, more efficient solution is to use fault-injection to emulate …
Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin
Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin
Faculty Publications
As process geometry sizes continue to decrease, microelectronics are becoming more vulnerable to the effects of radiation. Of particular concern are the effects of Single-Event Upsets (SEU) in Field Programmable Gate Arrays (FPGA). An SEU causes a dynamic memory element, such as a flip-flop or latch, to unwantedly change state. Since FPGAs are becoming an increasingly attractive solution for space system electronics, it is desirable to predict static on-orbit SEU rates likely to be encountered by a particular device for any particular orbit. Mean Time Between Failure (MTBF) can directly be calculated from a static SEU rate, allowing a system …
Higher Radix Floating-Point Representations For Fpga-Based Arithmetic, Bryan Christopher Catanzaro
Higher Radix Floating-Point Representations For Fpga-Based Arithmetic, Bryan Christopher Catanzaro
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are increasingly being used for high-throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an order of magnitude greater sustained floating-point throughput than conventional processors. FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations, as do general purpose processors. Binary representations were chosen as the standard over three decades ago because they provide maximal numerical accuracy per bit of floating-point data. However, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point …
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Theses and Dissertations
A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross …
A Flexible Circuit-Switched Communication Network For Fpga-Based Soc Design, Clint Richard Hilton
A Flexible Circuit-Switched Communication Network For Fpga-Based Soc Design, Clint Richard Hilton
Theses and Dissertations
As FPGA densities continue to improve, single chips are becoming capable of implementing larger and more complex systems. Even today these systems may include several processors working in conjuction with a handful of other standard interfaces or custom modules. Additional system complexity naturally leads to added complexity throughout the different design and implementation stages. Attempting to design such a system while maintaining high performance and within a reasonable time frame is becoming more and more difficult. Architectural design approaches ranging from direct module interconnection to sophisticated bus schemes have been used to build such systems, all with their own trade-offs. …
Reducing Energy In Fpga Multipliers Through Glitch Reduction, Nathaniel Rollins, Michael J. Wirthlin
Reducing Energy In Fpga Multipliers Through Glitch Reduction, Nathaniel Rollins, Michael J. Wirthlin
Faculty Publications
Sponsorship: NASA Earth Science Technology Office (ESTO). While FPGAs provide exibility for performing high-performance DSP functions, they consume a significant amount of power. For arithmetic circuits, a large portion of the dynamic power is wasted on unproductive signal glitches. Pipelining can be used to significantly reduce the unproductive power wasted in signal glitches. This paper presents a methodology for estimating the amount of power consumed by glitches and applies this methodology to non-pipelined, pipelined, and digit-serial multipliers. This glitch estimation is used to evaluate these multipliers using four energy metrics: energy per operation, energy delay, energy throughput, and energy density. …