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Full-Text Articles in Engineering
Memory Module Design For High-Temperature Applications In Sic Cmos Technology, Affan Abbasi
Memory Module Design For High-Temperature Applications In Sic Cmos Technology, Affan Abbasi
Graduate Theses and Dissertations
The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is …
A Robust Low Power Static Random Access Memory Cell Design, A. V. Rama Raju Pusapati
A Robust Low Power Static Random Access Memory Cell Design, A. V. Rama Raju Pusapati
Browse all Theses and Dissertations
Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin (SNM) of a cell, which determines the stability, varies under different operating conditions. Based on the performance of three existing SRAM cell designs, 6T, 8T and 10T, a 10 Transistor SRAM cell is proposed which has good stability and has the advantage of reduced read power when compared to 6T and 8T SRAM cells. The proposed 10T SRAM cell has a single-ended read circuit which improves SNM over the 6T cell. The proposed 10T cell …
Investigating Read/Write Aggregation To Exploit Power Reduction Opportunities Using Dual Supply Voltages, Gu Yunfei
McKelvey School of Engineering Theses & Dissertations
Power consumption plays an important role in computer system design today. On-chip memory structures such as multi-level cache make up a significant proportion of total power consumption of CPU or Application-Specific Integrated Circuit (AISC) chip, especially for memory-intensive application, such as floating-point computation and machine learning algorithm. Therefore, there is a clear motivation to reduce power consumption of these memory structures that are mostly consisting of Static Random-Access Memory (SRAM) blocks. In this defense, I will present the framework of a novel dual-supply-voltage scheme that uses separate voltage levels for memory read and write operations. By quantitatively analyzing the cache …
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
Theses and Dissertations
Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …
Sram Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies, Brandon Hilgers
Sram Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies, Brandon Hilgers
Master's Theses
This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with …
A Methodology Of Spice Simulation To Extract Sram Setup And Hold Timing Parameters Based On Dff Delay Degradation, Xiaowei Zhang
A Methodology Of Spice Simulation To Extract Sram Setup And Hold Timing Parameters Based On Dff Delay Degradation, Xiaowei Zhang
Theses and Dissertations--Electrical and Computer Engineering
SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the interface like multiple-level caches between high speed processing elements and low speed peripherals. One method to design the SRAM is to use commercial memory compiler. Such compiler can generate different density/speed SRAM designs with single/dual/multiple ports to fulfill design purpose. There are discrepancy of the SRAM timing parameters between extracted layout netlist SPICE simulation vs. equation-based Liberty file (.lib) by a commercial memory compiler. This compiler takes spec values as its input and uses them …
Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow
Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow
Graduate Theses and Dissertations
This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …