Engineering Commons^™

Reliability Analysis Of Nanocrystal Embedded High-K Nonvolatile Memories, Chia-Han Yang

Doctoral Dissertations

The evolution of the MOSFET technology has been driven by the aggressive shrinkage of the device size to improve the device performance and to increase the circuit density. Currently, many research demonstrated that the continuous polycrystalline silicon film in the floating-gate dielectric could be replaced with nanocrystal (nc) embedded high-k thin film to minimize the charge loss due to the defective thin tunnel dielectric layer.

This research deals with both the statistical aspect of reliability and electrical aspect of reliability characterization as well. In this study, the Zr-doped HfO₂ (ZrHfO) high-k MOS capacitors, which separately contain the nanocrystalline zinc …

Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt

Theses and Dissertations

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates …

On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes

Theses and Dissertations

This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory …

Managing Lithographic Variations In Design, Reliability, And Test Using Statistical Techniques, Aswin Sreedhar

Open Access Dissertations

Much of today's high performance computing engines and hand-held mobile devices are products of aggressive CMOS scaling. Technology scaling in semiconductor industry is mainly driven by corresponding improvements in optical lithography technology. Photolithography, the art used to create patterns on the wafer is at the heart of the semiconductor manufacturing process. Lately, improvements in optical technology have been difficult and slow. The transition to deep ultra-violet (DUV) light source (193nm) required changes in lens materials, mask blanks, light source and photoresist. It took more than ten years to develop a stable chemically amplified resist (CAR) for DUV. Consequently, as the …

Tin/Hfo2/Sio2/Si Gate Stacks Reliability : Contribution Of Hfo2 And Interfacial Sio2 Layer, Nilufa Rahim

Dissertations

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO₂ in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO₂) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO₂ gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the …

Design Issues In Magnetic Field Coupled Array: Clock Structure, Fabrication Defects And Dipolar Coupling, Anita Kumari

USF Tampa Graduate Theses and Dissertations

Even though silicon technology is dominant today, the physics (quantum electron tunneling effect), design (power dissipation, wire delays) and the manufacturing (lithography resolution) limitations of CMOS technology are pushed towards the scaling end. These issues motivated us towards a new paradigm that contributes to a continued advancement in terms of performance, density, and cost. The magnetic field coupled computing (MFC) paradigm, which is one of the regimes where we leverage and utilize the neighbor interaction of the nanomagnets to order the single-domain magnetic cells to perform computational tasks. The most important and attractive features of this technology are: 1) room …