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Electrical and Computer Engineering

LSU Master's Theses

Iddq testing

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Full-Text Articles in Engineering

[Delta] Iddq Testing Of A Cmos 12-Bit Charge Scaling Digital-To-Analog Converter, Kalyan Madhav Golla Jan 2006

[Delta] Iddq Testing Of A Cmos 12-Bit Charge Scaling Digital-To-Analog Converter, Kalyan Madhav Golla

LSU Master's Theses

This work presents design, implementation and test of a built-in current sensor (BICS) for ∆IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The sensor operates in two modes, the test mode and the normal mode. In the test mode, the BICS is connected to the circuit under test (CUT) which is DAC and detects abnormal currents caused by manufacturing defects. In the normal mode, BICS is isolated from the CUT. The BICS is integrated with the DAC and is implemented in a 0.5 μm n-well CMOS technology. …


Iddq Testing Of A Cmos 10-Bit Charge Scaling Digital-To-Analog Converter, Srinivas Rao Aluri Jan 2003

Iddq Testing Of A Cmos 10-Bit Charge Scaling Digital-To-Analog Converter, Srinivas Rao Aluri

LSU Master's Theses

This work presents an effective built-in current sensor (BICS), which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes the normal mode and the test mode. In the normal mode the BICS is isolated from the CUT due to which there is no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Further more our BICS can also distinguish the type of defect induced (Gate-source short, source-drain short and drain-gate short). Our BICS requires neither an external voltage …