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Ternary Logic To Binary Bit Conversion Using Multiple Input Floating Gate Mosfets In 0.5 Micron N-Well Cmos Technology, Sowmya Subramanian
Ternary Logic To Binary Bit Conversion Using Multiple Input Floating Gate Mosfets In 0.5 Micron N-Well Cmos Technology, Sowmya Subramanian
LSU Master's Theses
In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has been implemented in 0.5 µm n-well CMOS technology. The ternary input signals of {-1, 0, +1} are represented as -3 V, 0 V and +3 V, respectively. The ternary input is given as a combination of any two of the three voltage levels and the 4-bit binary output is generated in which the left most bit is sign bit (SB) followed by most significant bit (MSB), second significant bit (SSB) and the least significant bit …