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Current Transport Modeling Of Carbon Nanotube Field Effect Transistors For Analysis And Design Of Integrated Circuits, Jose Mauricio Marulanda Prado
Current Transport Modeling Of Carbon Nanotube Field Effect Transistors For Analysis And Design Of Integrated Circuits, Jose Mauricio Marulanda Prado
LSU Doctoral Dissertations
The purpose of this study was to develop a complete current transport model for carbon nanotube field effect transistors (CNT-FETs) applicable in the analysis and design of integrated circuits. The model was derived by investigating the electronic structure of carbon nanotubes and using basic laws of electrostatics describing a field effect transistor. We first derived analytical expressions for the carrier concentration in carbon nanotubes for different chiral vectors (n,m) by studying and characterizing their electronic structure. Results showed a strong relation to the diameter and wrapping angle of carbon nanotubes. The charge distribution in a CNT-FET is characterized from the …
Optimal Robust Fault Detection, Nike Liu
Optimal Robust Fault Detection, Nike Liu
LSU Doctoral Dissertations
This dissertation gives complete, analytic, and optimal solutions to several robust fault detection problems for both continuous and discrete linear systems that have been considered in the research community in the last twenty years. It is shown that several well-recognized robust fault detection problems, such as H_minus\H_2, H_2\ H_infinity and H_infinity\H_infinity problems, have a very simple optimal solution in an observer form by solving a standard algebraic Riccati equation. The optimal solutions to some other robust fault detection problems, such as H_minus\H_2 and H_2\H_2 problems are also given. In addition, it is shown that some well-studied and seeming sensible optimization …
Quiescent Current Testing Of Cmos Data Converters, Siva Yellampalli
Quiescent Current Testing Of Cmos Data Converters, Siva Yellampalli
LSU Doctoral Dissertations
Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of …