Engineering Commons^™

Semiconductor Yield Analysis And Prediction Using A Stochastic Layout Sensitivity Model, Rani S. Ghaida

Electrical and Computer Engineering ETDs

Spot defects represent the main challenge for enhancement of semiconductor manufacturing yield. As a result, the yield of modern integrated circuits is associated with the layout sensitivity to defects. The term layout sensitivity' is defined as the ratio of 'critical area', i.e. part of the layout in which a defect must be placed to cause a functional failure of the device, to the overall layout area. Semiconductor yield models are traditionally based on the analysis of the 'critical area'. Such models give accurate results; however, critical area analysis requires massive computations that render these models effort and time consuming. The …