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Des And Tdes Performance Evaluation For Non-Pipelined And Pipelined Implementations In Vhdl Using The Cyclone Ii Fpga Technology, Edni Del Rosal
Des And Tdes Performance Evaluation For Non-Pipelined And Pipelined Implementations In Vhdl Using The Cyclone Ii Fpga Technology, Edni Del Rosal
Theses and Dissertations
Two ongoing issues that engineers must face in the new era of data analytics are performance and security. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications while the Data Encryption Standard (DES) and the Triple Data Encryption Standard (TDES) offer a mean to secure information. In this thesis we present a Non-Pipelined and Pipelined, in Electronic Code Book (EBC) mode, implementations in VHDL of these two commonly utilized cryptography schemes. Using Altera Cyclone II FPGA as our platform, we design and verify the implementations with the EDA tools provided by Altera. We gather …