Engineering Commons^™

A Reconfigurable Architecture For Matrix Multiplication For Low Power Applications, Jeffrey Love

Electrical and Computer Engineering ETDs

This thesis presents a hardware architecture for performing matrix multiplication via a systolic array to reduce time complexity and power consumption. The proposed architecture, the Neural Network Accelerator (NNA), was designed in Verilog HDL to perform 8-bit multiplication to reduce the resources required to implement the NNA on low-power FPGAs. The NNA’s open architecture is designed to support radiation test for fault tolerant designs targeting space applications. Commercial hardware architecture information is not public knowledge, which led us to build our own matrix multiplication architecture so that we could later study its feasibility for space applications.

The NNA was compared …

Shift Register Puf Implementation On An Fpga, Sriram Thotakura

Electrical and Computer Engineering ETDs

In this thesis, a novel shift register-based physical unclonable function (PUF), called SRP, is proposed. The PUF is implemented on an FPGA and leverages the internal delay variations introduced by within-die process variations that occur within the Look-up tables (LUTs), routing and switches of the FPGA. PUFs are designed to generate bitstrings and keys on-the-fly that are device-specific (unique), random and reproducible. PUFs eliminate the need for a specialized (secure) non-volatile memory(NVM) to store the secret keys. This reduces the total cost of chips and systems, particularly those used in the Internet of Things, where it is common for systems …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …