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Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch
Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch
Bradley Minch
In this paper, we propose a modification to the class of circuits known as multiple input translinear element (MITE) networks. Our proposed modification leads to a MITE network that is free from certain nonidealities encountered in previous implementations. Further, the new MITE network described here readily accommodates the use of bipolar junction transistors in the input and output stages, thus implying a significantly wider dynamic range than we can achieve using subthreshold MOSFETs.
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
Bradley Minch
The author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, …
Floating-Gate Techniques For Assessing Mismatch, Bradley Minch
Floating-Gate Techniques For Assessing Mismatch, Bradley Minch
Bradley Minch
I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors. I also show experimental measurements of capacitor mismatch for small capacitors fabricated in 1.2-μm and 0.35-μm double-poly it n-well CMOS process that are commonly available.