Engineering Commons^™

System Efficient Esd Design Concept For Soft Failures, Giorgi Maghlakelidze

Doctoral Dissertations

"This research covers the topic of developing a systematic methodology of studying electrostatic discharge (ESD)-induced soft failures. ESD-induced soft failures (SF) are non-destructive disruptions of the functionality of an electronic system. The soft failure robustness of a USB3 Gen 1 interface is investigated, modeled, and improved. The injection is performed directly using transmission line pulser (TLP) with varying: pulse width, amplitude, polarity. Characterization provides data for failure thresholds and a SPICE circuit model that describes the transient voltage and current at the victim. Using the injected current, the likelihood of a SF is predicted. ESD protection by transient voltage suppressor …

On-Die Transient Event Sensors And System-Level Esd Testing, Abhishek Patnaik

Doctoral Dissertations

"System level electrostatic discharge (ESD) testing of electronic products is a critical part of product certification. Test methods were investigated to develop system level ESD simulation models to predict soft-failures in a system with multiple sensors. These methods rely completely on measurements. The model developed was valid only for the linear operation range of devices within the system. These methods were applied to a commercial product and used to rapidly determine when a soft failure would occur. Attaching cables and probes to determine stress voltages and currents within a system, as in the previous study, is time-consuming and can alter …

Characterization Of An Integrated Circuit With Respect To Electrostatic Discharge-Induced Soft Failures, Benjamin J. Orr

Doctoral Dissertations

"This research proposal presents a methodology whereby an integrated circuit (IC) can be characterized with respect to soft-failures induced by Electrostatic Discharge (ESD)-like events. This methodology uses an exclusively "black-box" approach to determine the response of an IC in a system-level environment, thereby allowing it to be implemented without intimate knowledge of the DUT IC. Results from this methodology can be referenced during system design to raise awareness of specific vulnerabilities of the core system ICs.

During work on this methodology, several sub topics have been explored and developed in the field of system-level ESD. Sections 2 and 3 introduce …