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Full-Text Articles in Engineering
A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher
A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher
Master's Theses
The SINDy (Sparse Identification of Non-linear Dynamics) algorithm is a method of turning a set of data representing non-linear dynamics into a much smaller set of equations comprised of non-linear functions summed together. This provides a human readable system model the represents the dynamic system analyzed. The SINDy algorithm is important for a variety of applications, including high precision industrial and robotic applications. A Hardware Accelerator was designed to decrease the time spent doing calculations. This thesis proposes an efficient hardware accelerator approach for a broad range of applications that use SINDy and similar system identification algorithms. The accelerator is …
General-Purpose Digital Filter Platform, Michael Cheng
General-Purpose Digital Filter Platform, Michael Cheng
Electrical Engineering
This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a …
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
Master's Theses
Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …
Fpga Based Bitcoin Mining, Philip Dotemoto
Fpga Based Bitcoin Mining, Philip Dotemoto
Electrical Engineering
This project attempts to implement an open source FPGA based Bitcoin miner on an Altera DE2-115 development board. Bitcoin is an experimental peer-to-peer digital currency based on public key cryptography. The advantages of Bitcoins are that they can be transferred between any two people anywhere in the world, and they do not have the same fees and lack of control associated with traditional methods of currency transfers. The first part of this project focuses on detailing how the Bitcoin network and open source miner work. The second part of the project attempts to improve the performance of the open source …
Applied Hw/Sw Co-Design: Using The Kendall Tau Algorithm For Adaptive Pacing, Kenneth W. Chee
Applied Hw/Sw Co-Design: Using The Kendall Tau Algorithm For Adaptive Pacing, Kenneth W. Chee
Master's Theses
Microcontrollers, the brains of embedded systems, have found their way into every aspect of our lives including medical devices such as pacemakers. Pacemakers provide life supporting functions to people therefore it is critical for these devices to meet their timing constraints. This thesis examines the use of hardware co-processing to accelerate the calculation time associated with the critical tasks of a pacemaker. In particular, we use an FPGA to accelerate a microcontroller’s calculation time of the Kendall Tau Rank Correlation Coefficient algorithm. The Kendall Tau Rank Correlation Coefficient is a statistical measure that determines the pacemaker’s voltage level for heart …
Digital Graphic Equalizer Implemented Using An Fpga, Anthony Giardina
Digital Graphic Equalizer Implemented Using An Fpga, Anthony Giardina
Electrical Engineering
A graphic equalizer is a device that adjusts the tonal quality of an audio signal. When sound is converted from a digital format to analog sound waves, there are amplification and transducing steps in-between the two formats. Common devices to perform these tasks are speakers, amplifiers, DACs, etc. Many of these devices exhibit a non-uniform frequency response over the range of human hearing. Thus, it is possible that certain frequency ranges of the audio signal will be amplified and others will be attenuated. To counteract this, an audio equalizer can be used to boost and attenuate certain frequency ranges within …
Global Positioning System, Vladimir Villalba
Global Positioning System, Vladimir Villalba
Electrical Engineering
The Global Positioning System (GPS) is a navigation network consisting of 24 satellites in orbit around the Earth. This satellite system provides the accurate position of an individual in all weather conditions at all times around the world. Individuals can use GPS receivers to locate where they are, pinpoint where they want to go with any form of transportation.
The senior project embarks in a path to understand the workings of the GPS satellite system. To accomplish this task, the concepts learned in Electrical Engineering will be implemented. This report encompasses the design process and steps taken in prototyping a …