Open Access. Powered by Scholars. Published by Universities.®
- Publication
- Publication Type
Articles 1 - 10 of 10
Full-Text Articles in Engineering
Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner
Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner
Faculty Publications
Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …
Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen
Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen
Theses and Dissertations
With a few exceptions, academic packing algorithms for FPGAs are typically applied solely to theoretical architectures. This has allowed the algorithms to focus on the basic components of packing while abstracting away many of the details dictated by real hardware. As commercially available FPGAs have advanced, however, the academic algorithms and architectures have diverged significantly from their commercial counterparts. In this dissertation, the RapidSmith 2 framework is presented. This framework accurately reflects the architecture of Xilinx FPGAs and provides support for integrating custom tools into the commercial CAD tools. Using this framework, the RSVPack packing algorithm is implemented. The RSVPack …
Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend
Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend
Theses and Dissertations
The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be extracted …
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
Theses and Dissertations
Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Theses and Dissertations
Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's …
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's …
Tincr: Integrating Custom Cad Tool Frameworks With The Xilinx Vivado Design Suite, Brad S. White
Tincr: Integrating Custom Cad Tool Frameworks With The Xilinx Vivado Design Suite, Brad S. White
Theses and Dissertations
The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FPGA devices. However, they are …
Power Side-Channel Dac Implementations For Xilinx Fpgas, Daniel Chase Savory
Power Side-Channel Dac Implementations For Xilinx Fpgas, Daniel Chase Savory
Theses and Dissertations
This thesis presents a novel power side-channel DAC (PS-DAC) which is constructed from user-controllable short circuits in FPGAs and which manipulate overall system power through dynamic power dissipation. Alternately, similar PS-DACs are created using shift-register primitives(SRL16E) which manipulate system power through switching logic, for means of comparison with short-circuit-based PS-DACs. PS-DACs are created of various sizes using both short-circuit-based and shift-register-based methods. These PS-DACs are characterized in terms of output linearity,monotonicity, and frequency distortion. Applications explored in this thesis which use PS-DAC technology include a Simple Power Analysis (SPA) side-channel transmitter, and a frequency watermarking application. These applications serve as …
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Theses and Dissertations
The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in terms of both time and money. As FPGAs scale to increased logical capacities, designers have increased flexibility. However, the FPGA placement problem becomes more difficult at increased sizes. Increasingly, designers are encouraged to structure designs hierarchically and floor-plan. Floor planning is a manual process which maps specified design submodules to selected physical regions of the FPGA device fabric. This thesis explores several of the effects that floor-planning has on submodules and the designs they comprise. A …
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Theses and Dissertations
Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the …