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Full-Text Articles in Engineering
Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon
Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon
Theses and Dissertations
Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the …
Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson
Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson
Theses and Dissertations
The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications. The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing can …
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
Theses and Dissertations
Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's …
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Theses and Dissertations
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Theses and Dissertations
Space destined FPGA-based systems must employ redundancy techniques to account for the effects of upsets caused by radiated environments. Error detection techniques can be used to alert external systems to the presence of these upsets. Readback with compare is an error detection technique commonly employed in FPGA-based designs. This work introduces duplication with compare (DWC) as an automated on-line error detection technique that can be used as an alternative to readback with compare. This work also introduces a set of metrics that is used to quantify the effectiveness and coverage of this error detection technique. A tool is presented that …
Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan
Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan
Theses and Dissertations
This thesis introduces a new way to characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section causes a temporary interruption of service, but in some cases this interruption may be tolerated. Techniques for measuring these cross sections are introduced. These cross sections can be measured and characterized for an arbitrary FPGA design. Furthermore, circuit components in the non-persistent and persistent cross section can statically be determined. Functional error …
Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin
Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin
Faculty Publications
Sponsorship: Los Alamos National Laboratory. Field Programmable Gate Arrays (FPGAs) are an attractive solution for space system electronics. Unfortunately, FPGAs are susceptible to radiation-induced single-event upsets (SEU). As such, the FPGA Reliability Studies research group (http://reliability.ee.byu.edu) at Brigham Young University has studied ways to effectively measure the static, dynamic and persistent cross sections of an FPGA desgin; each of which are characterized in some way by how the part reacts to an SEU. One such method is to actually radiate an FPGA and monitor how it reacts to SEUs. A cheaper, more efficient solution is to use fault-injection to emulate …
Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin
Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin
Faculty Publications
As process geometry sizes continue to decrease, microelectronics are becoming more vulnerable to the effects of radiation. Of particular concern are the effects of Single-Event Upsets (SEU) in Field Programmable Gate Arrays (FPGA). An SEU causes a dynamic memory element, such as a flip-flop or latch, to unwantedly change state. Since FPGAs are becoming an increasingly attractive solution for space system electronics, it is desirable to predict static on-orbit SEU rates likely to be encountered by a particular device for any particular orbit. Mean Time Between Failure (MTBF) can directly be calculated from a static SEU rate, allowing a system …
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Theses and Dissertations
A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross …