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Full-Text Articles in Engineering
Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner
Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner
Faculty Publications
Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …
Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon
Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon
Theses and Dissertations
Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the …
Optimization And Hardware Implementation Of Syba-An Efficient Feature Descriptor, Samuel Gaylin Fuller
Optimization And Hardware Implementation Of Syba-An Efficient Feature Descriptor, Samuel Gaylin Fuller
Theses and Dissertations
Feature detection, description and matching are crucial steps in many computer vision algorithms. These rely on feature descriptors to be able to match image features across sets of images. This paper discusses a hardware implementation and various optimizations of our lab's previous work on the SYnthetic BAsis feature descriptor (SYBA). Previous work has shown that SYBA can offer superior performance to other binary descriptors, such as BRIEF. This hardware implementation on an FPGA is a high throughput and low latency solution, which is critical for applications such as: high speed object detection and tracking, stereo vision, visual odometry, structure from …
Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson
Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson
Theses and Dissertations
The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications. The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing can …
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Theses and Dissertations
Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar …
Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen
Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen
Theses and Dissertations
Intellectual Property (IP) is used to speed up the design process and save money. The use of IP and complex CAD tools reduce visibility into the design and what is actually happening during synthesis and implementation. All of the complexity makes it easier for an attacker to insert malicious logic or tamper with the design in ways that are difficult to detect. Not very much work has been done towards the creation of tools to facilitate the safe use of 3rd-party IP. This work presents Physical and Functional Assurance, two approaches that aim to accomplish this task through physically and …
A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten
A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten
Theses and Dissertations
Embedded devices permeate our every day lives. They exist in our vehicles, traffic lights, medical equipment, and infrastructure controls. In many cases, improper functionality of these devices can present a physical danger to their users, data or financial loss, etc. Improper functionality can be a result of software or hardware bugs, but now more than ever, is often the result of malicious compromise and tampering, or as it is known colloquially "hacking". We are beginning to witness a proliferation of cyber-crime, and as more devices are built with internet connectivity (in the so called "Internet of Things"), security should be …
Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen
Academic Packing For Commercial Fpga Architectures, Travis D. Haroldsen
Theses and Dissertations
With a few exceptions, academic packing algorithms for FPGAs are typically applied solely to theoretical architectures. This has allowed the algorithms to focus on the basic components of packing while abstracting away many of the details dictated by real hardware. As commercially available FPGAs have advanced, however, the academic algorithms and architectures have diverged significantly from their commercial counterparts. In this dissertation, the RapidSmith 2 framework is presented. This framework accurately reflects the architecture of Xilinx FPGAs and provides support for integrating custom tools into the commercial CAD tools. Using this framework, the RSVPack packing algorithm is implemented. The RSVPack …
Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend
Vivado Design Interface: Enabling Cad-Tool Design For Next Generation Xilinx Fpga Devices, Thomas James Townsend
Theses and Dissertations
The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be extracted …
Using On-Chip Error Detection To Estimate Fpga Design Sensitivity To Configuration Upsets, Andrew Mark Keller
Using On-Chip Error Detection To Estimate Fpga Design Sensitivity To Configuration Upsets, Andrew Mark Keller
Theses and Dissertations
SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to …
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell
Theses and Dissertations
Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …
A Reconfigurable Trusted Platform Module, Matthew David James
A Reconfigurable Trusted Platform Module, Matthew David James
Theses and Dissertations
A Trusted Platform Module (TPM) is a security device included in most modern desktop and laptop computers. It helps keep the computing environment secure by isolating cryptographic functions and data from the CPU. A TPM is usually implemented with a small microcontroller which is near the main processor. In addition to a microcontroller, it may employ hardware acceleration to assist in cryptographic computations. When vulnerabilities are found, or new algorithms developed, TPMs become obsolete because the hardware accelerators cannot be upgraded. This thesis presents a proof of concept implementation of a TPM on an FPGA. By using an FPGA, the …
Duplicate With Choose: Using Statistics For Fault Mitigation, Jon-Paul Anderson
Duplicate With Choose: Using Statistics For Fault Mitigation, Jon-Paul Anderson
Theses and Dissertations
This dissertation presents a novel technique called duplicate with choose (DWCh) which is a modification of the fault detection technique duplicate with compare (DWC). DWCh adds a smart decider block to DWC that monitors the duplicated circuits and decides which circuit is fault free when a fault occurs. If chosen correctly, DWCh is able to mask faults at a lower cost than conventional techniques like TMR.This dissertation derives reliability expressions for DWCh showing that under ideal conditions its reliability exceeds the most commonly used fault masking technique for spacecraft, triple modular redundancy. For non-ideal conditions, DWCh provides a lower cost …
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Measuring Soft Error Sensitivity Of Fpga Soft Processor Designs Using Fault Injection, Nathan Arthur Harward
Theses and Dissertations
Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's …
Using Source-To-Source Transformations To Add Debug Observability To Hls-Synthesized Circuits, Joshua Scott Monson
Using Source-To-Source Transformations To Add Debug Observability To Hls-Synthesized Circuits, Joshua Scott Monson
Theses and Dissertations
This dissertation introduces a novel approach for exposing the internal, source-level expressions of circuits generated by high-level synthesis (HLS) for in-circuit debug. The approach uses source-to-source transformations to instrument specific source-level expressions with debug ports. These debug ports allow a user to connect a debugging instrument (e.g. an embedded logic analyzer) to record the activity of the expression corresponding to the debug port. This dissertation demonstrates that a debugging solution based on these source-to-source transformations is feasible and that individual debug ports can be added for a cost of a 1-2% increase in circuit area on average. It also introduces …
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Configuration Scrubbing Architectures For High-Reliability Fpga Systems, Aaron Gerald Stoddard
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's …
Address Space Translation For Fpga Accelerated Simulators, Michael Thaddeus Chamberlain
Address Space Translation For Fpga Accelerated Simulators, Michael Thaddeus Chamberlain
Theses and Dissertations
Microarchitectural simulation is needed to help explore the large design space of new computer systems. These simulations are taking increasingly longer amounts of time to run due to the increasing complexity of modern processors. Co-simulation and high level synthesis are promising fields to improve the overall time required for microarchitectural simulators, and can contribute to low design times and fast simulation speeds permitting a larger range of design space exploration. While promising, co-simulation techniques must find effective ways to map the host memory address space to the FPGA memory address space to be able to correctly transfer simulation data between …
Preemptive Placement And Routing For In-Field Fpga Repair, Joshua E. Jensen
Preemptive Placement And Routing For In-Field Fpga Repair, Joshua E. Jensen
Theses and Dissertations
With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This thesis presents a method for preemptively preparing to repair FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found …
Tincr: Integrating Custom Cad Tool Frameworks With The Xilinx Vivado Design Suite, Brad S. White
Tincr: Integrating Custom Cad Tool Frameworks With The Xilinx Vivado Design Suite, Brad S. White
Theses and Dissertations
The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FPGA devices. However, they are …
Single Event Mitigation For Aurora Protocol Based Mgt Fpga Designs In Space Environments, Alexander Stanley Harding
Single Event Mitigation For Aurora Protocol Based Mgt Fpga Designs In Space Environments, Alexander Stanley Harding
Theses and Dissertations
This work has extended an existing Aurora protocol for high-speed serial I/O between FPGAs to provide greater fault recovery in the presence of high-energy radiation. To improve on the Aurora protocol, additional resets that affect larger portions of the system were used. Detection for additional error modes that occurred but were not detected by the Aurora protocol was designed. Radiation testing was performed on the Aurora protocol with the additional mitigation hardware. The test gathered large amounts of data on the various error modes of the Aurora protocol and how the additional mitigation circuitry affected the system. The test results …
Power Side-Channel Dac Implementations For Xilinx Fpgas, Daniel Chase Savory
Power Side-Channel Dac Implementations For Xilinx Fpgas, Daniel Chase Savory
Theses and Dissertations
This thesis presents a novel power side-channel DAC (PS-DAC) which is constructed from user-controllable short circuits in FPGAs and which manipulate overall system power through dynamic power dissipation. Alternately, similar PS-DACs are created using shift-register primitives(SRL16E) which manipulate system power through switching logic, for means of comparison with short-circuit-based PS-DACs. PS-DACs are created of various sizes using both short-circuit-based and shift-register-based methods. These PS-DACs are characterized in terms of output linearity,monotonicity, and frequency distortion. Applications explored in this thesis which use PS-DAC technology include a Simple Power Analysis (SPA) side-channel transmitter, and a frequency watermarking application. These applications serve as …
Interface Design And Synthesis For Structural Hybrid Microarchitectural Simulators, Zhuo Ruan
Interface Design And Synthesis For Structural Hybrid Microarchitectural Simulators, Zhuo Ruan
Theses and Dissertations
Computer architects have discovered the potential of using FPGAs to accelerate software microarchitectural simulators. One type of FPGA-accelerated microarchitectural simulator, namedthe hybrid structural microarchitectural simulator, is very promising. This is because a hybrid structural microarchitectural simulator combines structural software and hardware, and this particular organization provides both modeling flexibility and fast simulation speed. The performance of a hybrid simulator is significantly affected by how the interface between software and hardware is constructed. The work of this thesis creates an infrastructure, named Simulator Partitioning Research Infrastructure (SPRI), to implement the synthesis of hybrid structural microarchitectural simulators which includes simulator partitioning, simulator-to-hardware …
Real-Time Color Treebasis Feature Matching On A Limited-Resource Hardware System, Garrett Sean Hartman
Real-Time Color Treebasis Feature Matching On A Limited-Resource Hardware System, Garrett Sean Hartman
Theses and Dissertations
This research has been conducted in order to create a robust, lightweight feature detecting and matching algorithm that builds upon the foundation set by the TreeBASIS algorithm. The goal is to create a color-based version of the TreeBASIS algorithm that uses less hardware resources than the original, is more accurate in its matching capabilities, can successfully be deployed on a resource-limited FPGA platform, and can process in real time. This thesis first presents the newly designed hardware tri-channel FAST Feature Detector that finds features in color. Next the TreeBASIS algorithm is analyzed to discover what improvements can be made in …
Reliability Techniques For Data Communication And Storage In Fpga-Based Circuits, Yubo Li
Reliability Techniques For Data Communication And Storage In Fpga-Based Circuits, Yubo Li
Theses and Dissertations
This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests then show that the proposed synchronizers provide between 6 and 10 orders of magnitude longer mean time to failure (MTTF) …
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Theses and Dissertations
The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in terms of both time and money. As FPGAs scale to increased logical capacities, designers have increased flexibility. However, the FPGA placement problem becomes more difficult at increased sizes. Increasingly, designers are encouraged to structure designs hierarchically and floor-plan. Floor planning is a manual process which maps specified design submodules to selected physical regions of the FPGA device fabric. This thesis explores several of the effects that floor-planning has on submodules and the designs they comprise. A …
Limited Resource Feature Detection, Description, And Matching, Spencer G. Fowers
Limited Resource Feature Detection, Description, And Matching, Spencer G. Fowers
Theses and Dissertations
The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a real-world challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed. CDoG provides better results than gray scale DoG and …
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Theses and Dissertations
Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. …
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Theses and Dissertations
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Theses and Dissertations
Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the …
Improved Stereo Vision Methods For Fpga-Based Computing Platforms, Wade S. Fife
Improved Stereo Vision Methods For Fpga-Based Computing Platforms, Wade S. Fife
Theses and Dissertations
Stereo vision is a very useful, yet challenging technology for a wide variety of applications. One of the greatest challenges is meeting the computational demands of stereo vision applications that require real-time performance. The FPGA (Field Programmable Gate Array) is a readily-available technology that allows many stereo vision methods to be implemented while meeting the strict real-time performance requirements of some applications. Some of the best results have been obtained using non-parametric stereo correlation methods, such as the rank and census transform. Yet relatively little work has been done to study these methods or to propose new algorithms based on …