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Engineering Commons

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Electrical and Computer Engineering

Brigham Young University

2023

Design Verification

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Full-Text Articles in Engineering

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner Dec 2023

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner

Faculty Publications

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …