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Genetic Algorithm Amplifier Biasing System (Gaabs): Genetic Algorithm For Biasing On Differential Analog Amplifiers, Sean Whalen

Computer Engineering

Genetic Algorithm Amplifier Biasing System (GAABS) - Senior Project Analysis

Summary of Functional Requirements

This project integrates LTSpice with a python script that runs a genetic algorithm to bias a differential amplifier. The system biases the amplifier with 2 different voltages, the base voltage for the PNP BJTs of the active loads and a voltage controlling the current of the current sink. The project runs via a python script, gets data from LTSpice’s command line call, and iteratively runs until the system is biased to achieve the greatest gain on an arbitrary input voltage.

Primary Constraints

Some of the main …

Modular Injection System And Sampling Template (M.I.S.S.T) Design Report, Froylan M. Aguirre

Computer Engineering

Digital systems are ubiquitous throughout modern life and their applications continue to grow. Thus system designers engineer and test modular systems to mitigate error rates. Smaller systems and their increasing importance in many applications demand the utmost reliability. Fault injection is the most common method used by researchers and engineers to test system reliability. However, most hardware fault injection implementations are ad hoc and only used to test a specific system or for specific tests. There is also software-implemented fault injection that adds overhead in the benchmark source code. The aim of this project is to develop a general use, …

Bicycle Power Meter, Andrew Mcguan

Computer Engineering

A power meter is a cycling training tool used to record the power a rider is outputting. This is very useful to athletes who regularly do bike workouts, because the power output is a consistent measure of the rider’s effort level, and is not affected by outside factors such as wind or road gradient. If a cyclist does a workout with the intent to carry a certain speed for a certain amount of time, a strong headwind will slow them down and make them work harder to maintain the same speed, defeating the goal of the workout. When a power …

Arm Mke1xf Mcu Replatform, Nathan Hong, Derek Lung, Japsimran Singh, Bevin Tang

Computer Engineering

After Cal Poly Racing’s electrical team began to hit the technical limits of the ADC and other I/O features of the current 8-bit Atmel AT90 microcontroller unit, it became clear that an upgrade was due. This replatforming project takes the functionalities of the old, 8-bit architecture, and aims to provide a 32-bit version using the ARM MKE1xF MCU. With the idea of having a working PCB as a stretch goal, the scope of the library development was limited to enable base functionality. Thus, the only libraries developed were for the Timer, ADC, SPI, UART, and CAN. Additionally, this document discusses …

Analog Sorting Using Pulse Width Modulation, Riley C. Olson

Computer Engineering

As time goes on, computers become more and more powerful. However, as processing time becomes less of a limiting factor for computing tasks, power consumption takes its place for many tasks. This paper proposes and tests a new method for sorting analog signals. This new sorting method converts analog signals into Pulse Width Modulated(PWM) signals of varying duty cycle , which are then sorted by a simple network of combinational logic, and then converted to a normal binary representation. In order to implement this new method, multiple circuits had to be designed and and tested to ensure their functionality and …

A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar

Computer Engineering

This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in …