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Articles 1 - 10 of 10
Full-Text Articles in Engineering
Reinventing Integrated Photonic Devices And Circuits For High Performance Communication And Computing Applications, Venkata Sai Praneeth Karempudi
Reinventing Integrated Photonic Devices And Circuits For High Performance Communication And Computing Applications, Venkata Sai Praneeth Karempudi
Theses and Dissertations--Electrical and Computer Engineering
The long-standing technological pillars for computing systems evolution, namely Moore's law and Von Neumann architecture, are breaking down under the pressure of meeting the capacity and energy efficiency demands of computing and communication architectures that are designed to process modern data-centric applications related to Artificial Intelligence (AI), Big Data, and Internet-of-Things (IoT). In response, both industry and academia have turned to 'more-than-Moore' technologies for realizing hardware architectures for communication and computing. Fortunately, Silicon Photonics (SiPh) has emerged as one highly promising ‘more-than-Moore’ technology. Recent progress has enabled SiPh-based interconnects to outperform traditional electrical interconnects, offering advantages like high bandwidth density, …
Cross-Layer Design Of Highly Scalable And Energy-Efficient Ai Accelerator Systems Using Photonic Integrated Circuits, Sairam Sri Vatsavai
Cross-Layer Design Of Highly Scalable And Energy-Efficient Ai Accelerator Systems Using Photonic Integrated Circuits, Sairam Sri Vatsavai
Theses and Dissertations--Electrical and Computer Engineering
Artificial Intelligence (AI) has experienced remarkable success in recent years, solving complex computational problems across various domains, including computer vision, natural language processing, and pattern recognition. Much of this success can be attributed to the advancements in deep learning algorithms and models, particularly Artificial Neural Networks (ANNs). In recent times, deep ANNs have achieved unprecedented levels of accuracy, surpassing human capabilities in some cases. However, these deep ANN models come at a significant computational cost, with billions to trillions of parameters. Recent trends indicate that the number of parameters per ANN model will continue to grow exponentially in the foreseeable …
A Flexible Photonic Reduction Network Architecture For Spatial Gemm Accelerators For Deep Learning, Bobby Bose
A Flexible Photonic Reduction Network Architecture For Spatial Gemm Accelerators For Deep Learning, Bobby Bose
Theses and Dissertations--Electrical and Computer Engineering
As deep neural network (DNN) models increase significantly in complexity and size, it has become important to increase the computing capability of specialized hardware architectures typically used for DNN processing. The major linear operations of DNNs, which comprise the fully connected and convolution layers, are commonly converted into general matrix-matrix multiplication (GEMM) operations for acceleration. Specialized GEMM accelerators are typically employed to implement these GEMM operations, where a GEMM operation is decomposed into multiple vector-dot-product operations that run in parallel. A common challenge that arises in modern DNNs is the mismatch between the matrices used for GEMM operations and the …
Energy Harvesting And Sensor Based Hardware Security Primitives For Cyber-Physical Systems, Carson Labrado
Energy Harvesting And Sensor Based Hardware Security Primitives For Cyber-Physical Systems, Carson Labrado
Theses and Dissertations--Electrical and Computer Engineering
The last few decades have seen a large proliferation in the prevalence of cyber-physical systems. Although cyber-physical systems can offer numerous advantages to society, their large scale adoption does not come without risks. Internet of Things (IoT) devices can be considered a significant component within cyber-physical systems. They can provide network communication in addition to controlling the various sensors and actuators that exist within the larger cyber-physical system. The adoption of IoT features can also provide attackers with new potential avenues to access and exploit a system's vulnerabilities. Previously, existing systems could more or less be considered a closed system …
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
Theses and Dissertations--Electrical and Computer Engineering
LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.
Hierarchical Implementation Of Aggregate Functions, Pablo Quevedo
Hierarchical Implementation Of Aggregate Functions, Pablo Quevedo
Theses and Dissertations--Electrical and Computer Engineering
Most systems in HPC make use of hierarchical designs that allow multiple levels of parallelism to be exploited by programmers. The use of multiple multi-core/multi-processor computers to form a computer cluster supports both fine-grain and large-grain parallel computation. Aggregate function communications provide an easy to use and efficient set of mechanisms for communicating and coordinating between processing elements, but the model originally targeted only fine grain parallel hardware. This work shows that a hierarchical implementation of aggregate functions is a viable alternative to MPI (the standard Message Passing Interface library) for programming clusters that provide both fine grain and large …
Efficient Anonymous Biometric Matching In Privacy-Aware Environments, Ying Luo
Efficient Anonymous Biometric Matching In Privacy-Aware Environments, Ying Luo
Theses and Dissertations--Electrical and Computer Engineering
Video surveillance is an important tool used in security and environmental monitoring, however, the widespread deployment of surveillance cameras has raised serious privacy concerns. Many privacy-enhancing schemes have been recently proposed to automatically redact images of selected individuals in the surveillance video for protection. To identify these individuals for protection, the most reliable approach is to use biometric signals as they are immutable and highly discriminative. If misused, these characteristics of biometrics can seriously defeat the goal of privacy protection. In this dissertation, an Anonymous Biometric Access Control (ABAC) procedure is proposed based on biometric signals for privacy-aware video surveillance. …
Power-Efficient And Low-Latency Memory Access For Cmp Systems With Heterogeneous Scratchpad On-Chip Memory, Zhi Chen
Theses and Dissertations--Electrical and Computer Engineering
The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this thesis focuses on proposing a new heterogeneous scratchpad memory architecture which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms, a dynamic programming and a genetic algorithm, to perform data allocation to different memory …
Fpga-Based Implementation Of Dual-Frequency Pattern Scheme For 3-D Shape Measurement, Brent Bondehagen
Fpga-Based Implementation Of Dual-Frequency Pattern Scheme For 3-D Shape Measurement, Brent Bondehagen
Theses and Dissertations--Electrical and Computer Engineering
Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface topology, phase information can be calculated and a 3D model constructed. Phase Measuring Profilometry (PMP) is a particular type of SLI that requires three or more patterns temporarily multiplexed. High speed PMP attempts to scan moving objects whose motion is small so as to have little impact on the 3-D model. Given that practically all machine vision cameras and high speed cameras employ a Field Programmable Gate Array (FPGA) interface directly to the image sensors, …
A Comprehensive Hdl Model Of A Line Associative Register Based Architecture, Matthew A. Sparks
A Comprehensive Hdl Model Of A Line Associative Register Based Architecture, Matthew A. Sparks
Theses and Dissertations--Electrical and Computer Engineering
Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.