Engineering Commons^™

Memory Optimizations For High-Throughput Computer Systems, Zhiyuan Lu

Dissertations, Master's Theses and Master's Reports

The emergence of new non-volatile memory (NVM) technology and deep neural network (DNN) inferences bring challenges related to off-chip memory access. Ensuring crash consistency leads to additional memory operations and exposes memory update operations on the critical execution path. DNN inference execution on some accelerators suffers from intensive off-chip memory access. The focus of this dissertation is to tackle the issues related to off-chip memory in these high performance computing systems.

The logging operations, required by the crash consistency, impose a significant performance overhead due to the extra memory access. To mitigate the persistence time of log requests, we introduce …

Eager Scheduling Of Dependent Instructions, Kurush Kasad

Dissertations, Master's Theses and Master's Reports

Modern superscalar processors are able to potentially issue and execute multiple instructions per cycle. Several techniques over the years have focused on increasing the Instruction Level Parallelism (ILP) that a processor can exploit. However, there are many limitations of ILP that hinder performance, chief of them being the chain of dependencies between instructions that stops instructions from being executed in parallel.

We propose a new micro-architecture design which extends the superscalar pipeline with a data-flow pipeline where the dataflow part identifies immediately dependent instructions and executes them early. The dataflow pipeline is able to identify redundant instructions, track changes in …

Demand-Driven Execution Using Future Gated Single Assignment Form, Omkar Javeri

Dissertations, Master's Theses and Master's Reports

This dissertation discusses a novel, previously unexplored execution model called Demand-Driven Execution (DDE), which executes programs starting from the outputs of the program, progressing towards the inputs of the program. This approach is significantly different from prior demand-driven reduction machines as it can execute a program written in an imperative language using the demand-driven paradigm while extracting both instruction and data level parallelism. The execution model relies on an executable Single Assignment Form which serves both as the internal representation of the compiler as well as the Instruction Set Architecture (ISA) of the machine. This work develops the instruction set …

Dynamic Dependency Collapsing, Görkem Aşılıoğlu

Dissertations, Master's Theses and Master's Reports

In this dissertation, we explore the concept of dynamic dependency collapsing. Performance increases in computer architecture are always introduced by exploiting additional parallelism when the clock speed is fixed. We show that further improvements are possible even when the available parallelism in programs are exhausted. This performance improvement is possible due to executing instructions in parallel that would ordinarily have been serialized. We call this concept dependency collapsing. We explore existing techniques that exploit parallelism and show which of them fall under the umbrella of dependency collapsing. We then introduce two dependency collapsing techniques of our own. The first technique …

Mitigating The Effect Of Misspeculations In Superscalar Processors, Zhaoxiang Jin

Dissertations, Master's Theses and Master's Reports

Modern superscalar processors highly rely on the speculative execution which speculatively executes instructions and then verifies. If the prediction is different from the execution result, a misspeculation recovery is performed. Misspeculation recovery penalties still account for a substantial amount of performance reduction. This work focuses on the techniques to mitigate the effect of recovery penalties and proposes practical mechanisms which are thoroughly implemented and analyzed.

In general, we can divide the misspeculation penalty into four parts: misspeculation detection delay; stale instruction elimination delay; state restoration delay and pipeline fill delay. This dissertation does not consider the detection delay, instead, we …

A Testbed Design For Monitoring The Long-Term Spatial-Temporal Dynamics Of Underwater Acoustic Channels, Krishna Chaitanya Poduru

Dissertations, Master's Theses and Master's Reports

The underwater acoustic network testbed helps to validate the theoretical results and bridge the gap between experimental results. Characterizing and modeling the spatial-temporal dynamics of underwater acoustic channels is essential to developing efficient and effective physical-layer communication algorithms and network protocols. This work dedicates to designing a testbed system to measure the spatial-temporal dynamics of underwater acoustic channels. The collected measurements will shed insights into the spatial-temporal correlation of underwater acoustic channels and will be used to evaluate the theoretical algorithms that are designed to model the spatial-temporal dynamics and to exploit the spatial-temporal dynamics for more efficient and effective …