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Full-Text Articles in Engineering
Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang
Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang
Electrical & Computer Engineering Faculty Research
ue to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across wired and wireless networks. Though supporting DiffServ scheduling algorithms for output-queuing (OQ) switches have been widely studied, there are few DiffServ scheduling algorithms for input-queuing (IQ) switches in the literaure. In this paper, we propose two algorithms for scheduling DiffServ DiffServ networks with IQ switches: the dynamic DiffServ scheduling (DDS) algorithm and the hierarchical DiffServ scheduling (HDS) algorithm. The basic idea of DDS and HDS is to schedule EF and AF traffic According to Their minimum service rates with the reserved bandwidth …
Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen
Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen
Electrical & Computer Engineering Faculty Research
We introduce the notion of free region of a node in a sensor network. Intuitively, a free region of a node is the connected set of points R in its neighborhood such that the connectivity of the network remains the same when the node is moved to any point in R. We characterize several properties of free regions and develop an efficient algorithm for computing them. We capture free region in terms of related notions called in-free region and out-free region. We present an O(n2) algorithm for constructing the free region of a node, where n is the number of …
Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng
Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng
Electrical & Computer Engineering Faculty Research
Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line …