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Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
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The move to more parallel computing architectures places more responsibility on the programmer to achieve greater performance. The programmer must now have a greater understanding of the underlying architecture and the inherent algorithmic parallelism. Using parallel computing architectures for exploiting algorithmic parallelism can be a complex task. This dissertation demonstrates various techniques for using parallel computing architectures to exploit algorithmic parallelism. Specifically, three pattern recognition (PR) approaches are examined for acceleration across multiple parallel computing architectures, namely field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPGPUs).
Phase-only filter correlation for fingerprint identification was studied as the first …
Performance Analysis And Fitness Of Gpgpu And Multicore Architectures For Scientific Applications, Mohammad Bhuiyan
Performance Analysis And Fitness Of Gpgpu And Multicore Architectures For Scientific Applications, Mohammad Bhuiyan
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Recent trends in computing architecture development have focused on exploiting task- and data-level parallelism from applications. Major hardware vendors are experimenting with novel parallel architectures, such as the Many Integrated Core (MIC) from Intel that integrates 50 or more x86 processors on a single chip, the Accelerated Processing Unit from AMD that integrates a multicore x86 processor with a graphical processing unit (GPU), and many other initiatives from other hardware vendors that are underway.
Therefore, various types of architectures are available to developers for accelerating an application. A performance model that predicts the suitability of the architecture for accelerating an …