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A Vhdl Design Of A Jpeg Still Image Compression Standard Decoder, Douglas Carpenter
A Vhdl Design Of A Jpeg Still Image Compression Standard Decoder, Douglas Carpenter
Theses
Digital images require large amounts of memory to be stored in a computer system. The JPEG compression standard allows the amount of memory storage required by a digital image to be reduced with little to no perceptible loss of image quality. This thesis is a design of an ASIC that implements a decoder of JPEG compressed images. The decoder implements the baseline decoder defined by the JPEG standard with a few exceptions, the most notable being that only grayscale images can be decompressed. With such an ASIC, the speed of decompressing images is greatly increased. The decoder was designed by …
Design And Implementation Of A Real-Time Morphological Image Processor Prototype, Jens Rodenberg
Design And Implementation Of A Real-Time Morphological Image Processor Prototype, Jens Rodenberg
Theses
Morphology, the study of form and structure, is also a method used for processing images. Morphological image processing can be used for many purposes, including edge detection, shape recognition, smoothing, and enhancement of images. A prototype for a real-time Morphological Image Processor has been developed to process 512 x 512 extended 8-bit gray scale images, using a 7 x 7 extended 8-bit gray scale mask. This prototype processor was developed jointly with another M.S. thesis candidate, Jeffrey Hanzlik. Software was also developed to allow the user to conveniently use a personal computer to transfer images to and from the Morphological …
Human Face Profile Recognition, Vincent Wong
Human Face Profile Recognition, Vincent Wong
Theses
The purpose of this thesis is to implement an automatic person identification system based on face profiles. Each person's face profile can be quite unique within a small sample population and therefore it can be used as the basis of an automatic person identification system. To quantify human face profiles for use in the recognition system, Fourier descriptors are used to describe the open curve extracted from a face profile. Fourier descriptors in the low-frequency range are shown to be useful for human face profile recognition. By using 16 Fourier coefficients, a correct recognition rate of 92% for 60 subjects …
Heuristics For Selecting Gray Scale Morphological Structuring Elements, Paul Fetter
Heuristics For Selecting Gray Scale Morphological Structuring Elements, Paul Fetter
Theses
This thesis explores some heuristics for choosing 8 bit gray scale morphological structuring elements for reducing noise. The variables of size, shape and volume that enter into the choice of structuring elements create a very large number of possible structuring elements. Some general heuristics to guide the choice of an appropriate structuring element will make the task easier. Both the absolute error of the image and the appearance of the image will be used to judge the results. The experiments were performed on 3 images. Each of the images had noise added before processing; one set of data had 10 …
A High Speed 16-Bit Risc Processor Chip, Wan-Fu Chen
A High Speed 16-Bit Risc Processor Chip, Wan-Fu Chen
Theses
The goal of this thesis is to design and simulate a high speed 16-bit processor chip by using RISC architecture. The high computing speed is achieved by employing a more effective four-stage pipeline. This processor executes every instruction in one clock cycle, and it won't have any delay of executing instructions when it executes Jump, Condition Jump, Call, and Return instructions. Its computing speed is 4 times faster than the speed of the Berkeley RISC II's for the 8-MHz clock. The design includes the main architectural features of the RISC: the 4-stage pipeline, the thirty-two 8-bit register bank, the 16-bit …
Vhdl Modeling And Design Of An Asynchronous Version Of The Mips R30000 Microprocessor, Paul Fanelli
Vhdl Modeling And Design Of An Asynchronous Version Of The Mips R30000 Microprocessor, Paul Fanelli
Theses
The goal of this thesis is to demonstrate the feasibility of converting a synchronous general purpose microprocessor design into one using an asynchronous methodology. This thesis is one of three parts that details the entire design of an asynchronous version of the MIPS R3000 microprocessor. The design includes the main architectural features of the R3000: the 5-stage pipeline, the thirty-two 32-bit register bank, and the 32-bit address and data paths. To limit the size of the project, the memory and coprocessor are excluded. Therefore, this design has implemented the entire set of instructions from the original synchronous version with the …