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Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Fast Sobel Edge Detection Using Parallel Pipeline-Based Architecture On Fpga, Mohammad Shokrolah Shirazi, Brendan Morris
Fast Sobel Edge Detection Using Parallel Pipeline-Based Architecture On Fpga, Mohammad Shokrolah Shirazi, Brendan Morris
College of Engineering: Graduate Celebration Programs
Implementing image processing algorithms on FPGA has recently become more popular since it provides high speed in comparison with software-based approaches. In this paper, we have presented fast pipeline-based architecture for one of the most popular edge detection algorithms called Sobel edge detection. The objective of our work is to present two fast pipeline-based architectures for Sobel edge detection on FPGA benefiting one and two way parallelism. We used Verilog language to implement our designs and we synthesized each one for Cyclone IV FPGA. Experimental results show that our pipeline-based architectures perform edge detection process more than 379 and 751 …