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The Electrical Characterization Of Sic Jfets In High Temperature And Neutron Radiation Environments, Robert Oakley
The Electrical Characterization Of Sic Jfets In High Temperature And Neutron Radiation Environments, Robert Oakley
Theses
During initial analysis of Silicon Carbide (SiC) based field effect devices, testing apparatus and methodologies were developed and implemented to characterize the effects of neutron radiation and high temperatures on the devices. This paper will discuss the development of these methodologies and the apparatus fabricated to conduct the testing. Also discussed will be the state of the art of SiC at the time of the testing and a summary of the relevant radiation effects physics and device physics used in the development of the testing apparatus and methodologies. A summary of the effectiveness of the test apparatus and methodologies and …
Efficient Vhdl Models For Various Pld Architectures, Vassilis Giannopoulos
Efficient Vhdl Models For Various Pld Architectures, Vassilis Giannopoulos
Theses
VHDL is a flexible language for programming PLDs (Programmable Logic Devices) but the way it is synthesized for different architectures varies. Since there are several types of PLDs and several synthesis tools, it is very important for the designer to know which VHDL model to use for a particular architecture in order to achieve maximum efficiency. The term efficiency refers to a good use of resources that result to a denser fit of the logic design into the PLD with a minimum implementation delay. The choice of the VHDL model also depends on the application and the expectations of the …
Methods For Minimizing Performance Degradation Caused By Branch Delays, Debbie St. Onge
Methods For Minimizing Performance Degradation Caused By Branch Delays, Debbie St. Onge
Theses
The presence of branch instructions in an instruction stream may adversely affect the performance of a processor by introducing significant delays in the execution process. As processors become more pipelined, the impact these delays have upon performance increases. This thesis investigates why delays occur when branch instructions are encountered. It also summarizes various hardware methodologies which can alleviate the performance degradation due to these delays. Simulation results show that these hardware methodologies can improve branch performance by up to 45 percent. Some branches are inherently necessary in order to implement programming decisions. However, the use of branches within programs can …
A Cmos Monolithic Analog Multiplier With Wide Input Dynamic Range, George Anthony Hadgis
A Cmos Monolithic Analog Multiplier With Wide Input Dynamic Range, George Anthony Hadgis
Theses
A novel CMOS monolithic analog multiplier capable of operating in two quadrants is described in this thesis. The multiplier incorporates a voltage-controlled variable linear resistor comprised of two FET transistors in the feedback network of an operational amplifier. This novel approach to implementing an analog multiplier results in good linearity and wide input dynamic range when compared to other implementations where an FET is incorporated in the feedback network of an operational amplifier. The analog multiplier, comprised of an operational amplifier and a variable linear resistor, has been designed. PSpice simulation results are given in support of the multiplier. Experimental …
The Influence Of Locos-Related Oxide Etch On Thin Oxide Leakage In Memory Devices, Rohan Braithwaite
The Influence Of Locos-Related Oxide Etch On Thin Oxide Leakage In Memory Devices, Rohan Braithwaite
Theses
The influence of oxide etch backs done in LOCOS based isolation technologies on the low level leakage and reliability of tunnel oxide capacitors has been studied. Tunnel oxide structures are part of nonvolatile memory devices such as Flash EEPROMs and are critical to their overall performance. Locos isolated, area and edge intensive capacitors with 94 A tunnel oxide have been manufactured and tested. Test results indicate that the extent of the etch back and the use of HF instead of buffered HF as chemical etchants do not adversely affect the low level leakge of the tunnel capacitors. However, oxide endurance …
Methods For Robust Designs: Applied To A High Impedance Bootstrapped Differential Amplifier, James Hossenlopp
Methods For Robust Designs: Applied To A High Impedance Bootstrapped Differential Amplifier, James Hossenlopp
Theses
This thesis demonstrates both analytical and statistical tools for robust design by applying them to a high impedance bootstrapped differential amplifier. This circuit example has only one free variable for optimization. Having a single free variable allows using optimization tools without requiring a volume for each analytical and statitstical method. The thesis is written in tutorial style and includes significant detail. The robust design tools applied are: - Analytical and Statistical Optimization - Analytical and Statistical Sensitivity Analysis - Analytical and Statistical Worst Case Analysis - Expectation Theory and Monte Carlo Distribution Analysis Other techniques that are used are: - …