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Strain Relaxation In Nm-Thick Cu And Cu-Alloy Films Bonded To A Rigid Substrate, Ashley Herrmann
Strain Relaxation In Nm-Thick Cu And Cu-Alloy Films Bonded To A Rigid Substrate, Ashley Herrmann
Legacy Theses & Dissertations (2009 - 2024)
In the wide scope of modern technology, nm-thick metallic films are increasingly used as lubrication layers, optical coatings, plating seeds, diffusion barriers, adhesion layers, metal contacts, reaction catalyzers, etc. A prominent example is the use of nm-thick Cu films as electroplating seed layers in the manufacturing of integrated circuits (ICs). These high density circuits are linked by on-chip copper interconnects, which are manufactured by filling Cu into narrow trenches by electroplating. The Cu fill by electroplating requires a thin Cu seed deposited onto high-aspect-ratio trenches. In modern ICs, these trenches are approaching 10 nm or less in width, and the …
Optical Metrology For Directed Self-Assembly Patterning Using Mueller Matrix Spectroscopic Ellipsometry Based Scatterometry, Dhairya J. Dixit
Optical Metrology For Directed Self-Assembly Patterning Using Mueller Matrix Spectroscopic Ellipsometry Based Scatterometry, Dhairya J. Dixit
Legacy Theses & Dissertations (2009 - 2024)
The semiconductor industry continues to drive patterning solutions that enable devices with higher memory storage capacity, faster computing performance, lower cost per transistors, and higher transistor density. These developments in the field of semiconductor manufacturing along with the overall minimization of the size of transistors require cutting-edge metrology tools for characterization.
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
An Assessment Of Critical Dimension Small Angle X-Ray Scattering Metrology For Advanced Semiconductor Manufacturing, Charles Michael Settens
Legacy Theses & Dissertations (2009 - 2024)
Simultaneous migration of planar transistors to FinFET architectures, the introduction of a plurality of materials to ensure suitable electrical characteristics, and the establishment of reliable multiple patterning lithography schemes to pattern sub-10 nm feature sizes imposes formidable challenges to current in-line dimensional metrologies. Because the shape of a FinFET channel cross-section immediately influences the electrical characteristics, the evaluation of 3D device structures requires measurement of parameters beyond traditional critical dimension (CD), including their sidewall angles, top corner rounding and footing, roughness, recesses and undercuts at single nanometer dimensions; thus, metrologies require sub-nm and approaching atomic level measurement uncertainty.