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Articles 1  30 of 47
FullText Articles in Engineering
Sparse Coding On Stereo Video For Object Detection, Sheng Y. Lundquist, Melanie Mitchell, Garrett T. Kenyon
Sparse Coding On Stereo Video For Object Detection, Sheng Y. Lundquist, Melanie Mitchell, Garrett T. Kenyon
Computer Science Faculty Publications and Presentations
Deep Convolutional Neural Networks (DCNN) require millions of labeled training examples for image classification and object detection tasks, which restrict these models to domains where such a dataset is available. We explore the use of unsupervised sparse coding applied to stereovideo data to help alleviate the need for large amounts of labeled data. In this paper, we show that unsupervised sparse coding is able to learn disparity and motion sensitive basis functions when exposed to unlabeled stereovideo data. Additionally, we show that a DCNN that incorporates unsupervised learning exhibits better performance than fully supervised networks. Furthermore, finding a sparse representation ...
Tetrahedral Mesh Optimization And Generation Via Topological Transformations And Gradient Based Node Perturbation, Christopher B. Hilbert
Tetrahedral Mesh Optimization And Generation Via Topological Transformations And Gradient Based Node Perturbation, Christopher B. Hilbert
Masters Theses and Doctoral Dissertations
A general tetrahedral mesh optimization scheme utilizing both topological changes (i.e. flips) and gradientbased vertex optimization (i.e. smoothing) is demonstrated. This scheme is used in the optimization of tetrahedral meshes created by thirdparty software as well as a grid generation methodology created for this work. The particular algorithms involved are explained in detail including, an explication of the primary optimization metric, weighted condition number. In addition, a thorough literature review regarding tetrahedral mesh generation is given.
A Theory Of Name Resolution, Pierre Néron, Andrew Tolmach, Eelco Visser, Guido Wachsmuth
A Theory Of Name Resolution, Pierre Néron, Andrew Tolmach, Eelco Visser, Guido Wachsmuth
Computer Science Faculty Publications and Presentations
We describe a languageindependent theory for name binding and resolution, suitable for programming languages with complex scoping rules including both lexical scoping and modules. We formulate name resolution as a twostage problem. First a languageindependent scope graph is constructed using languagespecific rules from an abstract syntax tree. Then references in the scope graph are resolved to corresponding declarations using a languageindependent resolution process. We introduce a resolution calculus as a concise, declarative, and language independent specification of name resolution. We develop a resolution algorithm that is sound and complete with respect to the calculus. Based on the resolution calculus we ...
Compressive Sensing Based Imaging Via Belief Propagation, Preethi Modur Ramachandra
Compressive Sensing Based Imaging Via Belief Propagation, Preethi Modur Ramachandra
Masters Theses and Doctoral Dissertations
Multiple description coding (MDC) using Compressive Sensing (CS) mainly aims at restoring an image from a small subset of samples with reasonable accuracy using an iterative message passing decoding algorithm commonly known as Belief Propagation (BP). The CS technique can accurately recover any compressible or sparse signal from a lesser number of nonadaptive, randomized linear projection samples than that specified by the Nyquist rate. In this work, we demonstrate how CSbased encoding generates measurements from the sparse image signal and the measurement matrix. Then we demonstrate how a BP decoding algorithm reconstructs the image from the measurements generated. In our ...
Resizable, Scalable, Concurrent Hash Tables, Josh Triplett, Paul E. Mckenney, Jonathan Walpole
Resizable, Scalable, Concurrent Hash Tables, Josh Triplett, Paul E. Mckenney, Jonathan Walpole
Computer Science Faculty Publications and Presentations
We present algorithms for shrinking and expanding a hash table while allowing concurrent, waitfree, linearly scalable lookups. These resize algorithms allow the hash table to maintain constanttime performance as the number of entries grows, and reclaim memory as the number of entries decreases, without delaying or disrupting readers.
We implemented our algorithms in the Linux kernel, to test their performance and scalability. Benchmarks show lookup scalability improved 125x over readerwriter locking, and 56% over the current stateoftheart for Linux, with no performance degradation for lookups during a resize.
To achieve this performance, this hash table implementation uses a new concurrent ...
Application Of Cuda In The Boolean Domain For The Unate Covering Problem, Eric Paul, Bernd Steinbach, Marek Perkowski
Application Of Cuda In The Boolean Domain For The Unate Covering Problem, Eric Paul, Bernd Steinbach, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
NVIDIA’s Compute Unified Device Architecture (CUDA) is a relativelyrecent development that allows to realize very fast algorithms for several Constraint Satisfaction and Computer Aided Design tasks. In this paper we present an approach to use Graphics Processing Units (GPU) and CUDA for solving Unate Covering Problem, a practical problem related to SAT. In particular we present a CUDAenabled Petrick Function Minimizer. We compare the performance of a pipelineprocessor (CPU) and a parallel processor (GPU) implementation of the matrixmultiplication method for solving unate covering problems.
Fully Anisotropic SplitTree Adaptive Refinement Mesh Generation Using Tetrahedral Mesh Stitching, Vincent Charles Betro
Fully Anisotropic SplitTree Adaptive Refinement Mesh Generation Using Tetrahedral Mesh Stitching, Vincent Charles Betro
Masters Theses and Doctoral Dissertations
Due to the myriad of geometric topologies that modern computational fluid dynamicists desire to mesh and run solutions on, the need for a robust Cartesian Mesh Generation algorithm is paramount. Not only do Cartesian meshes require less elements and often help resolve flow features but they also allow the grid generator to have a great deal of control in so far as element aspect ratio, size, and gradation. Fully Anisotropic SplitTree Adaptive Refinement (FASTAR) is a code that allows the user to exert a great deal of control and ultimately generate a valid, geometry conforming mesh. Due to the splittree ...
Waypoint Generation Based On Sensor Aimpoint, Shannon M. Farrell
Waypoint Generation Based On Sensor Aimpoint, Shannon M. Farrell
Theses and Dissertations
Secretary of Defense Robert M. Gates has emphasized a need for a greater number of intelligence, surveillance, and reconnaissance (ISR) assets to support combatant commanders and military operations globally. Unmanned systems, especially MAVs, used as ISR platforms provide the ability to maintain covertness during missions and help reduce the risk to human life. This research develops waypoint generation algorithms required to keep a point of interest (POI) in the field of view (FOV) of a fixed sensor on a micro air vehicle (MAV) in the presence of a constant wind.
Fixed sensors, while cheaper and less prone to mechanical failure ...
An Algorithm For Identifying Novel Targets Of Transcription Factor Families: Application To HypoxiaInducible Factor 1 Targets, Yue Jiang, Bojan Cukic, Donald A. Adjeroh, Heath D. Skinner, Jie Lin, Qingxi J. Shen, BingHua Jiang
An Algorithm For Identifying Novel Targets Of Transcription Factor Families: Application To HypoxiaInducible Factor 1 Targets, Yue Jiang, Bojan Cukic, Donald A. Adjeroh, Heath D. Skinner, Jie Lin, Qingxi J. Shen, BingHua Jiang
Electrical and Computer Engineering Faculty Publications
Efficient and effective analysis of the growing genomic databases requires the development of adequate computational tools. We introduce a fast method based on the suffix tree data structure for predicting novel targets of hypoxiainducible factor 1 (HIF1) from huge genome databases. The suffix tree data structure has two powerful applications here: one is to extract unknown patterns from multiple strings/sequences in linear time; the other is to search multiple strings/sequences using multiple patterns in linear time. Using 15 known HIF1 target gene sequences as a training set, we extracted 105 common patterns that all occur in the 15 ...
Significance Of Logic Synthesis In FpgaBased Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba
Significance Of Logic Synthesis In FpgaBased Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba
Electrical and Computer Engineering Faculty Publications
This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, generalpurpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally ...
Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj
Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj
Electrical and Computer Engineering Faculty Publications
Nesting algorithms deal with placing two dimensional shapes on the given canvas. In this paper a binary way of solving the nesting problem is proposed. Geometric shapes are quantized into binary form, which is used to operate on them. After finishing nesting they are converted back into original geometrical form. Investigations showed, that there is a big influence of quantization accuracy for the nesting effect. However, greater accuracy results with longer time of computation. The proposed knowledge base system is able to strongly reduce the computational time.
Use Of Tabu Search In A Solver To Map Complex Networks Onto Emulab Testbeds, Jason E. Macdonald
Use Of Tabu Search In A Solver To Map Complex Networks Onto Emulab Testbeds, Jason E. Macdonald
Theses and Dissertations
The University of Utah's solver for the testbed mapping problem uses a simulated annealing metaheuristic algorithm to map a researcher's experimental network topology onto available testbed resources. This research uses tabu search to find nearoptimal physical topology solutions to user experiments consisting of scalefree complex networks. While simulated annealing arrives at solutions almost exclusively by chance, tabu search incorporates the use of memory and other techniques to guide the search towards good solutions. Both search algorithms are compared to determine whether tabu search can produce equal or higher quality solutions than simulated annealing in a shorter amount of ...
Improved Hyperspectral Image Testing Using Synthetic Imagery And Factorial Designed Experiments, Joseph P. Bellucci
Improved Hyperspectral Image Testing Using Synthetic Imagery And Factorial Designed Experiments, Joseph P. Bellucci
Theses and Dissertations
The goal of any remote sensing system is to gather data about the geography it is imaging. In order to gain knowledge of the earth's landscape, postprocessing algorithms are developed to extract information from the collected data. The algorithms can be intended to classify the various ground covers in a scene, identify specific targets of interest, or detect anomalies in an image. After the design of an algorithm comes the difficult task of testing and evaluating its performance. Traditionally, algorithms are tested using sets of extensively ground truthed test images. However, the lack of well characterized test data sets ...
Ternary Quantum Logic, Normen Giesecke
Ternary Quantum Logic, Normen Giesecke
Dissertations and Theses
The application of Moore's Law would not be feasible by using the computing systems fabrication principles that are prevalent today. Fundamental changes in the field of computing are needed to keep Moore's Law operational. Different quantum technologies are available to take the advancement of computing into the future. Logic in quantum technology uses gates that are very different from those used in contemporary technology. Limiting itself to reversible operations, this thesis presents different methods to realize these logic gates. Two methods using Generalized Ternary Gates and Muthukrishnan Stroud Gates are presented for synthesis of ternary logic gates. Realizations ...
Image Quality Assessment Using Artificial Neural Networks, Alexander Havstad
Image Quality Assessment Using Artificial Neural Networks, Alexander Havstad
Theses: Doctorates and Masters
not available
A Fast And Simple Algorithm For Computing M Shortest Paths In Stage Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar
A Fast And Simple Algorithm For Computing M Shortest Paths In Stage Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar
Electrical and Computer Engineering Faculty Publications
We consider the problem of computing m shortest paths between a source node s and a target node t in a stage graph. Polynomial time algorithms known to solve this problem use complicated data structures. This paper proposes a very simple algorithm for computing all m shortest paths in a stage graph efficiently. The proposed algorithm does not use any complicated data structure and can be implemented in a straightforward way by using only array data structure. This problem appears as a subproblem for planning risk reduced multiple klegged trajectories for aerial vehicles.
Logic Synthesis For Layout Regularity Using Decision Diagrams, Malgorzata ChrzanowskaJeske, Alan Mishchenko, Jinsong Zhang, Marek Perkowski
Logic Synthesis For Layout Regularity Using Decision Diagrams, Malgorzata ChrzanowskaJeske, Alan Mishchenko, Jinsong Zhang, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents a methodology for logic synthesis of Boolean functions in the form of regular structures that can be mapped into standard cells or programmable devices. Regularity offers an elegant solution to hard problems arising in layout and test generation, at no extra cost or at the cost of increasing the number of gates, which does not always translate into the increase of circuit area. Previous attempts to synthesize logic into regular structures using decision diagrams suffered from an increase in the number of logic levels due to multiple repetitions of control variables. This paper proposes new techniques, which ...
A Fast And Simple Algorithm For Computing MShortest Paths In State Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar
A Fast And Simple Algorithm For Computing MShortest Paths In State Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar
Electrical and Computer Engineering Faculty Publications
We consider the problem of computing m shortest paths between a source node s and a target node t in a stage graph. Polynomial time algorithms known to solve this problem use complicated data structures. This paper proposes a very simple algorithm for computing all m shortest paths in a stage graph efficiently. The proposed algorithm does not use any complicated data structure and can be implemented in a straightforward way by using only array data structure. This problem appears as a subproblem for planning risk reduced multiple klegged trajectories for aerial vehicles.
FunctionDriven Linearly Independent Expansions Of Boolean Functions And Their Application To Synthesis Of Reversible Circuits, Pawel Kerntopf, Marek Perkowski
FunctionDriven Linearly Independent Expansions Of Boolean Functions And Their Application To Synthesis Of Reversible Circuits, Pawel Kerntopf, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
The paper presents a family of new expansions of Boolean functions called Functiondriven Linearly Independent (fLI) expansions. On the basis of this expansion a new kind of a canonical representation of Boolean functions is constructed: Functiondriven Linearly Independent Binary Decision Diagrams (fLIBDDs). They generalize both Functiondriven Shannon Binary Decision Diagrams (fShBDDs) and Linearly Independent Binary Decision Diagram (LIBDDs). The diagrams introduced in the paper, can provide significantly smaller representations of Boolean functions than standard Ordered Binary Decision Diagrams (OBDDs), Ordered Functional Decision Diagrams (OFDDs) and Ordered (Pseudo) Kronecker Functional Decision Diagrams (OKFDDs) and can be applied to synthesis of reversible ...
Logic Synthesis For Regular Layout Using Satisfiability, Marek Perkowski, Alan Mishchenko
Logic Synthesis For Regular Layout Using Satisfiability, Marek Perkowski, Alan Mishchenko
Electrical and Computer Engineering Faculty Publications and Presentations
In this paper, we propose a regular layout geometry called 3×3 lattice. The main difference of this geometry compared to the known 2×2 regular layout geometry is that it allows the cofactors on a level to propagate to three rather than two nodes on the lower level. This gives additional freedom to synthesize compact functional representations. We propose a SATbased algorithm, which exploits this freedom to synthesize 3×3 lattice representations of completely specified Boolean functions. The experimental results show that the algorithm generates compact layouts in reasonable time.
Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar
Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar
Electrical and Computer Engineering Faculty Publications
The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.
Implicit Algorithms For MultiValued Input Support Manipulation, Alan Mishchenko, Craig Files, Marek Perkowski, Bernd Steinbach, Christina Dorotska
Implicit Algorithms For MultiValued Input Support Manipulation, Alan Mishchenko, Craig Files, Marek Perkowski, Bernd Steinbach, Christina Dorotska
Electrical and Computer Engineering Faculty Publications and Presentations
We present an implicit approach to solve problems arising in decomposition of incompletely specified multivalued functions and relations. We introduce a new representation based on binaryencoded multivalued decision diagrams (BEMDDs). This representation shares desirable properties of MDDs, in particular, compactness, and is applicable to weaklyspecified relations with a large number of output values. This makes our decomposition approach particularly useful for data mining and machine learning. Using BEMDDs to represent multivalued relations we have developed two complementary input support minimization algorithms. The first algorithm is efficient when the resulting support contains almost all initial variables; the second is efficient when ...
BiDecomposition Of MultiValued Relations, Alan Mishchenko, Marek Perkowski, Bernd Steinbach
BiDecomposition Of MultiValued Relations, Alan Mishchenko, Marek Perkowski, Bernd Steinbach
Electrical and Computer Engineering Faculty Publications and Presentations
This presentation discusses an approach to decomposition of multivalued functions and relations into networks of twoinput gates implementing multivalued MIN and MAX operations. The algorithm exploits both the incompleteness of the initial specification and the flexibilities generated in the process of decomposition. Experimental results over a set of multivalued benchmarks show that this approach outperforms other approaches in the quality of final results and CPU time.
Development Of SelfAdaptive Back Propagation And Derivative Free Training Algorithms In Artificial Neural Networks, Shamsuddin Ahmed
Development Of SelfAdaptive Back Propagation And Derivative Free Training Algorithms In Artificial Neural Networks, Shamsuddin Ahmed
Theses: Doctorates and Masters
Three new iterative, dynamically selfadaptive, derivativefree and training parameter free artificial neural network (ANN) training algorithms are developed. They are defined as selfadaptive back propagation, multidirectional and restart ANN training algorithms. The descent direction in selfadaptive back propagation training is determined implicitly by a central difference approximation scheme, which chooses its step size according to the convergence behavior of the error function. This approach trains an ANN when the gradient information of the corresponding error function is not readily available. The self adaptive variable learning rates per epoch are determined dynamically using a constrained interpolation search. As a result, appropriate ...
Improving The Run Time Of The Decomposition Algorithm For Fault Tolerant Clos Interconnection Networks Through Swap ReOrdering, Andrea Laura Mcmakin
Improving The Run Time Of The Decomposition Algorithm For Fault Tolerant Clos Interconnection Networks Through Swap ReOrdering, Andrea Laura Mcmakin
Theses
Clos interconnection networks, used in data networks and computing systems, can contain extra switches to be used in faulty conditions. The speed of such fault tolerant Clos interconnection networks is improved through the use these switches in nofault situations. The network can be represented by a matrix, which is then decomposed using an algorithm, and the switch settings are thus assigned.
The original decomposition algorithm consisted of four element swaps in the following order: wild swap, simple swap, next simple swap, and successive swap. However, by rearranging these swaps with the simple swap first, followed by the next simple and ...
Dynamic Load Distribution In Mist, K. AlSaqabi, R. M. Prouty, Dylan Mcnamee, Steve Otto, Jonathan Walpole
Dynamic Load Distribution In Mist, K. AlSaqabi, R. M. Prouty, Dylan Mcnamee, Steve Otto, Jonathan Walpole
Computer Science Faculty Publications and Presentations
This paper presents an algorithm for scheduling parallel applications in largescale, multiuser, heterogeneous distributed systems. The approach is primarily targeted at systems that harvest idle cycles in generalpurpose workstation networks, but is also applicable to clustered computer systems and massively parallel processors. The algorithm handles unequal processor capacities, multiple architecture types and dynamic variations in the number of processes and available processors. Scheduling decisions are driven by the desire to minimize turnaround time while maintaining fairness among competing applications. For efficiency, the virtual processors (VPs) of each application are gang scheduled on some subset of the available physical processors.
Jitter And Wander Reduction For A Sonet Ds3 Desynchronizer Using Predictive Fuzzy Control, Kevin Blythe Stanton
Jitter And Wander Reduction For A Sonet Ds3 Desynchronizer Using Predictive Fuzzy Control, Kevin Blythe Stanton
Dissertations and Theses
Excessive highfrequency jitter or lowfrequency wander can create problems within synchronous transmission systems and must be kept within limits to ensure reliable network operation. The emerging Synchronous Optical NETwork (SONET) introduces additional challenges for jitter and wander attenuation equipment (called desynchronizers) when used to carry payloads from the existing Plesiochronous Digital Hierarchy (PDH), such as the DS3. The difficulty is primarily due to the large phase transients resulting from the pointerbased justification technique employed by SONET (called Pointer Justification Events or PJEs). While some previous desynchronization techniques consider the buffer level in their control actions, none has explicitly considered wander ...
Minimization Of SumOfConditionalDecoders Structures With Applications In Finite Machine Epld Design And Machine Learning, Sanof Mohamedsadakathulla
Minimization Of SumOfConditionalDecoders Structures With Applications In Finite Machine Epld Design And Machine Learning, Sanof Mohamedsadakathulla
Dissertations and Theses
In order to achieve superior speed in sequencer designs over competing PLD devices, Cypress brought to market an innovative architecture, CY7C361. This architecture introduced a new kind of universal logic gate, the CONDITION DECODER (CDEC). Because there are only 32 macrocells in the chip, saving only one CDEC gate can be quite important (the wellknown "fit/nofit problem"). A problem that is related to the fitting problem of the Cypress CY7C361 chip is the SOC Minimization. Due to the limited low number of macrocells in CY7C361, a high quality logic minimization to reduce the number of macrocells is very important ...
A General Approach To Boolean Function Decomposition And Its Application In Fpgabased Synthesis, Tadeusz Luba, Henry Selvaraj
A General Approach To Boolean Function Decomposition And Its Application In Fpgabased Synthesis, Tadeusz Luba, Henry Selvaraj
Electrical and Computer Engineering Faculty Publications
An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of rpartitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single or multipleoutput functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The ...
High Level Preprocessor Of A VhdlBased Design System, Karthikeyan Palanisamy
High Level Preprocessor Of A VhdlBased Design System, Karthikeyan Palanisamy
Dissertations and Theses
This thesis presents the work done on a design automation system in which highlevel synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL based DIADES system into a VHDL based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL based design system from Mentor Graphics. The highlevel synthesis in the DIADES system includes two stages: data path synthesis and control unit ...