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Full-Text Articles in Engineering
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Theses and Dissertations
Space destined FPGA-based systems must employ redundancy techniques to account for the effects of upsets caused by radiated environments. Error detection techniques can be used to alert external systems to the presence of these upsets. Readback with compare is an error detection technique commonly employed in FPGA-based designs. This work introduces duplication with compare (DWC) as an automated on-line error detection technique that can be used as an alternative to readback with compare. This work also introduces a set of metrics that is used to quantify the effectiveness and coverage of this error detection technique. A tool is presented that …
Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan
Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan
Theses and Dissertations
This thesis introduces a new way to characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section causes a temporary interruption of service, but in some cases this interruption may be tolerated. Techniques for measuring these cross sections are introduced. These cross sections can be measured and characterized for an arbitrary FPGA design. Furthermore, circuit components in the non-persistent and persistent cross section can statically be determined. Functional error …
Active Fpga Security Through Decoy Circuits, Bradley D. Christiansen
Active Fpga Security Through Decoy Circuits, Bradley D. Christiansen
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) based on Static Random Access Memory (SRAM) are vulnerable to tampering attacks such as readback and cloning attacks. Such attacks enable the reverse engineering of the design programmed into an FPGA. To counter such attacks, measures that protect the design with low performance penalties should be employed. This research proposes a method which employs the addition of active decoy circuits to protect SRAM FPGAs from reverse engineering. The effects of the protection method on security, execution time, power consumption, and FPGA resource usage are quantified. The method significantly increases the security of the design with …
Fpga-Based Experiment Platform For Hardware-Software Codesign And Hardware Emulation, Yajuvendra Nagaonkar
Fpga-Based Experiment Platform For Hardware-Software Codesign And Hardware Emulation, Yajuvendra Nagaonkar
Theses and Dissertations
An FPGA-based experiment platform for hardware-software codesign experiments was developed. The proposed platform would be used by an engineer who can be affiliated with academia, research or industry for codesign experiments or hardware emulation. The platform utilizes a combination of a microcontroller and a FPGA device to enable sufficient flexibility in exploring the design space to implement codesign experiments. The FPGA device operation is integrated with that of the microcontroller to provide an overall embedded solution for codesign experimentations. It is anticipated that the platform will be used in academia for educating the students the concepts of computer architecture and …
Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-Programmable Gate Arrays, Anuja Thakkar
Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-Programmable Gate Arrays, Anuja Thakkar
Electronic Theses and Dissertations
Many space applications, such as vision-based systems, synthetic aperture radar, and radar altimetry rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the tradition in DSP processing has been to use fixed point number representation, only recently have DSP processors begun to incorporate floating point arithmetic units, even though most of these units handle only single precision floating point addition/subtraction, multiplication, …
Fpga Frequency Domain Based Gps Coarse Acquisition Processor Using Fft, Cyprian D. Sajabi
Fpga Frequency Domain Based Gps Coarse Acquisition Processor Using Fft, Cyprian D. Sajabi
Browse all Theses and Dissertations
The Global Positioning System or GPS is a satellite based technology that has gained widespread use worldwide in civilian and military applications. Direct Sequence Spread spectrum (DSSS) is the method whereby the data transmitted by the satellite and received by user is kept secure, low power and relatively noise-immune. The first step required in the GPS operation is to perform a lock on the incoming signal, both with respect to time synchronization and frequency resolution. Because of the need for reduced time to lock and also reduced hardware, algorithms based in the frequency domain have been developed. These algorithms take …
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
Browse all Theses and Dissertations
Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an …