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Full-Text Articles in Engineering
Minimization Of Exclusive Sum Of Products Expressions For Multiple-Valued Input Incompletely Specified Functions, Ning Song
Dissertations and Theses
In recent years, there is an increased interest in the design of logic circuits which use EXOR gates. Particular interest is in the minimization of arbitrary Exclusive Sums Of Products (ESOPs). Functions realized by such circuits can have fewer gates, fewer connections, and take up less area in VLSI and especially, FPGA realizations. They are also easily testable. So far, the ESOPs are not as popular as their Sum of Products (SOP) counterparts. One of the main reasons it that the problem of the minimization of ESOP circuits was traditionally an extremely difficult one. Since exact solutions can be practically …
Effectiveness Of Additive Correction Multigrid In Numerical Heat Transfer Analysis When Implemented On An Intel Ipsc2, James D. Padgett
Effectiveness Of Additive Correction Multigrid In Numerical Heat Transfer Analysis When Implemented On An Intel Ipsc2, James D. Padgett
Dissertations and Theses
The effectiveness of the Additive Correction Multigrid (ACM) algorithm, a line-byline Tri-diagonal Matrix Algorithm (TDMA), and simple Gauss-Seidel (GS) iteration in numerical heat transfer analysis is investigated on a conventional single processor computer and on a distributed memory parallel computer. The performance of these methods is studied by solving a two-dimensional, steady heat conduction problem. The execution time of ACM on a single processor is proportional to the number of unknowns to the 1.5 power. This is in contrast to the execution time of the TDMA for which the execution time is proportional to the number of unknowns to the …
Mapping Programs To Parallel Architectures In The Real World, Dezheng Tang
Mapping Programs To Parallel Architectures In The Real World, Dezheng Tang
Dissertations and Theses
Mapping an application program to a parallel architecture can be described as a multidimensional optimization problem. To simplify the problem, we divide the overall mapping process into three sequential substeps: partitioning, allocating, and scheduling, with each step using a few details of the program and architecture description. Due to the difficulty in accurately describing the program and architecture and the fact that each substep uses incomplete information, inaccuracy is pervasive in the real-world mapping process. We hypothesize that the inaccuracy and the use of suboptimal, heuristic mapping methods may greatly affect the mapping or submapping performance and lead to a …
Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan
Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan
Dissertations and Theses
The goal of parallel processing is to achieve high speed computing by partitioning a program into concurrent parts, assigning them in an efficient way to the available processors, scheduling the program and then executing the concurrent parts simultaneously. In the past researchers have combined the allocation of tasks in a program and scheduling of those tasks into one operation. We define scheduling as a process of efficiently assigning priorities to the already allocated tasks in a program. Assignment of priorities is important in cases when more than one task at a processor is ready for execution. Most heuristics for scheduling …
A Partitioning-Based Approach To The Fitting Problem In Special Architecture Eplds, Steffan Goller
A Partitioning-Based Approach To The Fitting Problem In Special Architecture Eplds, Steffan Goller
Dissertations and Theses
In this thesis, we describe an architecture-driven fitting algorithm for an Application-Specific EPLD, the CY7C361, from Cypress Semiconductor. Traditional placement and routing tools for PLDs perform placement and routing separately. Several placement possibilities are created and the router tries to realize the connections between the physical locations of the cells on the chip. The Cypress CY7C361 has a very unique chip architecture with a highly limited connectivity between the physical cells. Therefore, it is necessary to consider the mutability when the placement of cells is performed. The combination of the two stages is called fitting. The specific architecture-dependent constraints, imposed …
Improved I/O Pad Positions Assignment Algorithm For Sea-Of-Gates Placement, Shyang-Kuen Her
Improved I/O Pad Positions Assignment Algorithm For Sea-Of-Gates Placement, Shyang-Kuen Her
Dissertations and Theses
A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a predecessor of PROUD. The results …