Digital Commons Network^™

Improving The Scalability And Usability Of The Public Information Officer Monitoring Application, Rohan D. Shah

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

This thesis work addresses the limitations of a web application called the Public Information Officer Monitoring Application (PMA). This application helps Public Information Officers (PIOs) to gather, monitor, sort, store, and report social media data during a crisis event. Before this work, PMA was unable to handle large data sets and as a result, it had not been adequately tested with potential users of the application.

This thesis describes changes made to PMA to improve its ability to handle large data sets. After these changes were made, the application was then tested with target users. All test participants found the …

Tackling Voltage Emergencies In Noc Through Timing Error Resilience., Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy

Electrical and Computer Engineering Faculty Publications

Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.

Design Of Reliable And Secure Network-On-Chip Architectures, Dean Michael B Ancajas

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues. This dissertation demonstrates design techniques that address both reliability and security issues facing modern NoC architectures. The reliability and security problem is tackled at different abstraction levels using a series of schemes that combine information from the architecture-level as well as hardware-level in order to combat aging effects and meet secure design stipulations while maintaining modest power-performance overheads.